clock: msm: Add clk support for second qcrypto device

Add clock entry for a second qcrypto instance for 8974.

Change-Id: I6e4c6e32e62c5cf26992c7d0dc8b27b188c2b15c
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
hammerhead: Add clk support for second qcrypto device

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
crypto: msm: add suspend/resume callback for qcedev driver

Make chanegs to add suspend/resume callback for qcedev driver, and
disable ce clocks when entering suspend and re-enable clocks in resume.

Change-Id: Ibeab1e7cb531af79ae973d7ff0d0ed2d776f6d6f
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: William Clark <wclark@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
qseecom: Verify shared buffer size

Valiade ION allocated shared buffer mapped in kernel space
is of same size as allocated in user space.

Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
crypto:msm: Remove excess logging in qce50

During device probe, device tree is called & the
device tree details are logged - these logs
are now truncated.

Change-Id: I0a6f45cbd4717ded1ef515e3e76452397826d240
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: fix aead combined mode decipher problem

Fix -EBADMSG error for crypto 5.1 and above for aead decipher.
bam dma input/output length should include asso data plus iv plus crypto
data, and excluding MAC result for deciphering.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
ARM: gic: use a private mapping for CPU target interfaces

The GIC interface numbering does not necessarily follow the logical
CPU numbering, especially for complex topologies such as multi-cluster
systems.

Fortunately we can easily probe the GIC to create a mapping as the
Interrupt Processor Targets Registers for the first 32 interrupts are
read-only, and each field returns a value that always corresponds to
the processor reading the register.

Initially all mappings target all CPUs in case an IPI is required to
boot secondary CPUs.  It is refined as those CPUs discover what their
actual mapping is.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
slim_msm_ngd: Add IPC logging support

Add IPC logging support for improved debugging
per device, and in memory to avoid using kernel
dmesg logs.

Logs are captured in four levels.
1) error level ---> All fatal errors are logged
2) warn level  ---> error level logs +
Warning messages are logged
3) Info level  ---> Error level +
warn level + the required information
for debugging is logged
4) Debug level ----> error level + warn level +
info level logs + extra information
for debugging are logged

Procedure to change the debug level at runtime:
==============================================
cd sys/devices/ctrl_num(eg:1234).slim
echo <log_level> > debug_mask

Procedure to collect the logs at run time:
=========================================
adb shell cat sys/kernel/debug/ipc_logging/ctrl_num.slim/log_cont
|tee slimbus.txt

CRs-Fixed: 645838
Change-Id: If183533472ee61b2d8cf458d228dd4ae2124dd37
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ngd_slim: Decouple clock pause from power down/up

NGD slimbus driver itself can never send out clock pause sequence
for slimbus protocol on the HW lines since it can only be sent by
a manager device (which is controlled by ADSP when NGD driver is
instantiated from apps side).
Previously, clock pause of slimbus framework was coupled with power
down/up. That is not correct, since manager device may or may not
decide to send clock-pause on the HW lines. (e.g. if apps is inactive,
but some client on ADSP is active, clock-pause sequence won't be sent
over the bus.
Decouple power-on/off from clock pause to avoid giving incorrect
impression to clients on apps side about clock-pause state. Mark
clock-pause as unsupported by setting wakup function pointer to NULL
instead since this controller on apps cannot send it on HW lines.

CRs-Fixed: 667165
Change-Id: I382bca153deb2fed1d0f0672adaebde1e122dc68
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register

The ISAR0 register indicates support for the SDIV and UDIV
instructions in both the Thumb and ARM instruction set. Read the
register to detect the supported instructions and update the
elf_hwcap mask as appropriate. This is better than adding more
and more cpuid checks in proc-v7.S for each new cpu variant that
supports these instructions.

Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
ARM: dma-mapping: Add maximum alignment order for dma iommu buffers

Alignment order for a dma iommu buffer is set by buffer size. For
large buffer, it is a waste of iommu address space. So configurable
parameter to limit maximum alignment order can reduce the waste.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin.park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUs

Some early versions of the Krait CPU design incorrectly indicate
that they only support the UDIV and SDIV instructions in Thumb
mode when they actually support them in ARM and Thumb mode. It
seems that these CPUs follow the DDI0406B ARM ARM which has two
possible values for the divide instructions field, instead of the
DDI0406C document which has three possible values.

Work around this problem by checking the MIDR against Krait CPUs
with this faulty ISAR0 register and force the hwcaps to indicate
support in both modes.

[sboyd: Rewrote commit text to reflect real reasoning now that
	we autodetect udiv/sdiv]

Change-Id: I3d3ea2075c450cea50ccecb3904a4304ef6cc1d8
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
ARM: 7660/1: tlb: add branch predictor maintenance operations

The ARM architecture requires explicit branch predictor maintenance
when updating an instruction stream for a given virtual address. In
reality, this isn't so much of a burden because the branch predictor
is flushed during the cache maintenance required to make the new
instructions visible to the I-side of the processor.

However, there are still some cases where explicit flushing is required,
so add a local_bp_flush_all operation to deal with this.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead

Many ARMv7 cores have hardware page table walkers that can read the L1
cache. This is discoverable from the ID_MMFR3 register, although this
can be expensive to access from the low-level set_pte functions and is a
pain to cache, particularly with multi-cluster systems.

A useful observation is that the multi-processing extensions for ARMv7
require coherent table walks, meaning that we can make use of ALT_SMP
patching in proc-v7-* to patch away the cache flush safely for these
cores.

Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2

commit bf3f0f332f76a85ff3a0b393aaded5a8533769c0 upstream.

Commit ae8a8b9553bd ("ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE
and use ALT_SMP instead") added early function returns for page table
cache flushing operations on ARMv7 SMP CPUs.

Unfortunately, when targetting Thumb-2, these `mov pc, lr' sequences
assemble to 2 bytes which can lead to corruption of the instruction
stream after code patching.

This patch fixes the alternates to use wide (32-bit) instructions for
Thumb-2, therefore ensuring that the patching code works correctly.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>
msm: ocmem: Serialize allocation requests only when necessary

Certain clients of ocmem always have exclusive regions set aside in
the OCMEM memory map. Allocation requests for such clients do not
have to wait for any pending evictions in progress to be completed
nor will trigger any new evictions and can be safely scheduled right
away.

Signed-off-by: Naveen Ramaraj <nramaraj@codeaurora.org>
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: ocmem: Do not use data mover for clearing ocmem memory

In the non secure environment the data mover is used to clear
the ocmem memory. The ocmem driver no longer uses the data
mover for this operation.

Signed-off-by: Neeti Desai <neetid@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: ocmem: Add macro and region size information to ocmem region

Some targets support half sized macros in the last region. Previously,
for these regions, only half the macros were turned on, and the clients
could not access memory. Read the hardware register to check if the
target supports half sized macros and update the calculation to switch
memory power states.

Change-Id: Idb6e6b8c11b42d3e0a72fa27bd8c63e48282af97
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: ocmem: Call restore_sec_config() after every power collapse

As the QRIB is enabled, after every power collapse of ocmem, the
QRIB is reset to the maximum security state. Due to this the apps
processor cannot access the ocmem register space.

The restore_sec_config() scm call needs to be called before any
register is accessed after a power collapse to ensure that the
security configuration is restored. The clocks need to be turned
on before every call that is made into TZ to ensure that there
is no power collapse.

CRs-Fixed: 651324, 660089
Change-Id: Ieb6b635142057e219de29e811c93749f6500cec5
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: Fix NULL pointer dereference in sensors ADSP driver.

Memory is allocated on the heap via kzalloc for temp variable.
Then it is passed through error checking. Error checking is
incorrect however, because instead of immediately returning -ENOMEM,
the function continues without returning. temp could be potentially
NULL when passed in to memcpy, causing a NULL dereference and writing
to that location.

Change-Id: Ib9faef2a542d1d8da35e1b3f7292596c9bddadba
CRs-fixed: 563553
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Chet Kener <Cl3Kener@gmail.com>