[pcie_hdl] Switch to using OHWR general-cores whenever possible.
This will allow greater code reuse and greater flexibility over using
COREGEN generated FIFO & BRAM modules.
Changes to DDRs_Control module are still needed, but will happen a bit
later as this module needs some refactoring.
[pcie_hdl] Cleanup some dead code & update .xise project files.
[pcie_hdl]Switch to level triggering to fix deadlock
in TLP preprocessing FSM.