cappuccino/lsu: let stores go through to dcache when disabled

In case the cache is temporarily disabled, stores to cache hits
still have to be performed in to the cache.
icache: minor whitespace cleanup
icache: move refill ibus logic to fetch

A fair amount of logic in the icache is used to handle
the bus access logic for refills, by moving this logic into the
fetch module (which also need the bus access logic for non-cache
accesses), a bit of resources can be saved.

This only moves the bus access logic, the icache still serves
as a 'master' that initiates the refill.
It might be beneficial to 'dumb-down' the icache even more
and let the fetch module completely control the refill
(and invalidation).
icache: hold refill_request_o

In case the fetch unit can't immediately serve the refill request,
the signal has to be held high until it can.
dcache: move refill dbus logic to lsu

As in the similar rework for icache/fetch, the motivation for
this is to save some resources.
An added benefit here is that it *should* also untangle
a pretty critical path going through dc_access out on the dbus
via dbus_adr. With the mux that created that path gone,
hopefully there should be some improvements in timing as well.
dcache: remove extraneous ';'
dcache: remove extraneous ';'
pic: make NMIs configurable

That the bottom two irqs are NMIs is something that comes from
the or1200 implementation, there is nowhere stated in the arch
spec about them.
This makes the number of NMIs configurable, to allow backwards
compatibility with or1200, but at the same time, the default
is changed to disable them.
alu: add alternative non-stall "PIPELINED" mul impementation

The "PIPELINED" mul implementation is similar to the
"THREESTAGE" implementation, but with the difference that
instead of stalling the pipeline while the multiply is performed
in execute stage, the pipelining of the multiply go 'along' with
the cpu pipeline.
I.e. the multiply operation will be finished in write-back stage,
and the result muxed directly into the register-file.

This comes with the following implications:
The two following instructions after the multiply
instruction can't have their input forwarded from
execute stage nor ctrl/mem stage. Instead, nop-bubbles
are inserted on such occations.

Since the result is not ready in execute stage,
generating multiply overflows becomes cumbersome and
has therefore been omitted.

While this gives a significant boost in multiply operations,
a multiply now takes (best case) 1 cycle instead of 3
(and coremark score sees about a 4% boost),
timing reports show worse timing score with this implementation.
However the worst critical paths looks unrelated to the
multiplier, so some further work here is needed.

On the other hand, comparing resource usage between the
"PIPELINED" and "THREESTAGE" implementations,
the "PIPELINED" takes less resources.
decode: do not generate illegal insn exception on l.msync

l.msync is a class II instruction, which means that it is
optional to implement.
However, this doesn't mean that the instruction should
generate an illegal instruction exception when it's not
implemented, instead the arch spec states that it should
instead be implemented as a no-op on implementations
that has strongly ordered memory accesses.

To be consistent, parameters are added for all three
sync instructions, l.msync, l.psync and l.csync.
None of them have actual implementations, and l.psync and
l.csync will generate illegal insn exceptions when their
parameters are defined as "NONE".
propagate OPTION_PIC_NMI_WIDTH all the way up to top level

This was accidently omitted when the OPTION_PIC_NMI_WIDTH
parameter was introduced.
cfgrs: whitespace cleanup and switch to verilog2001 module declaration
add support for shadow register files

This adds an additional parameter, that configure the number
of shadow register files are present.
This functionality is related to the fast contexts, but
that feature is not yet implemented.

Software can however make use of the shadowed rf without
the fast context functionality, by reading and writing the
shadowed register file by spr accesses.
Reading the RF over spr was already supported,
but this also adds write support.
cappuccino/lsu: perform stores to cache during cache inhibit

To keep the cache memory coherent under the situation
where a system writes to a cache-inhibit memory area
while the dmmu is on, but reads from it when it is off,
writes have to go through to the cache in case of a hit.
cappuccino: move reading of rf port A to decode

The benefit of this is that it makes it possible to add an extra
registering stage between decode and execute, avoiding some
critical paths that comes from adding a lot of logic straight to
the rf RAM outputs.

This also allows for the PIPELINED multiplier to hook up
to the outputs at decode stage, to be able to add an extra
registering stage to the end of that.

The disadvantage is that extra forwarding logic is
needed between decode and execute.
cappuccino/decode: fix PIPELINED multiplier interlocks

ctrl_to_decode interlock needs to cover both port a and b
cappuccino/fetch: latch rf address on bus_access_done

Since the pipeline is advanced on this signal, the register
file gating should follow that.
cappuccino/decode: make branch indicate signal more lightweigth

decode_bubble_o is a very heavy weight signal to depend on,
the only time decode_bubble_o can be asserted when there
is a branch instruction in decode stage is when there is
either an instruction in ctrl/mem stage or execute stage
producing a result that is needed by the branch.

Explicitly use that condition in the branch_to_reg signal.
cappuccino: move overflow disable to execute_alu

This will set the originating signals to zero when
FEATURE_OVERFLOW is "NONE".
make carry flag optional with FEATURE_CARRY_FLAG

The carry flag (SR[CY]) is mandatory by the spec, but
is rarely used by software.
This makes it possible to disable the support for it to
save resources and untangle some potential critical paths.

Currently only cappuccino actually disables the support upon
setting the FEATURE_CARRY_FLAG parameter to "NONE".