xula2 upload commonly requires root
buildsys: force gmake failure for more targets
buildsys: allow sim-only HDL file lists
allow extending bitfile list on a per-board basis
buildsys: par_ and map_timing PHONY corrections
buildsys: DEFAULT not DEFAULT_GOAL
buildsys: hack to ensure correct target is selected
buildsys: don't actually need to copy around .ngc's
fix bitfile outputs
quick start: commit all the things
zed: restyle example makefile tb_verilog_files comment
microzed: by default TIG reset net
microzed: more headers; also 50mhz?
microzed: active high reset in template
fix isim target (remove 'simulate')
lint: add color, recursive include, Xilinx primitives

All subdirectories below ./hdl are now added to the lint search path.
%Error and %Warning get colorized.
Xilinx Unisim primitives use empty template definitions; errors in this
file are ignored using a verilator config file.
remove duplicate 'make help' entry
better 'make help' header
zynq: dos2unix zed and uzed ucf files
fix isim target (remove 'simulate')