Fix 'dram_tpr3' reporting

Get it from the dllcr registers instead of always returning 0.
Fix 'dram_clk' reporting for frequencies that are not multiples of 24

The K and M factors encode values 1-4 in two bits (starting from 1
and not 0). The typical DRAM clock frequency setup uses K=2 and M=2,
which means that both of them are read as 1 from the bit fields.
That's why a10-meminfo used to work in most cases (1/1 is the same
as 2/2). However a10-meminfo happens to report wrong 'dram_clk' if
the other values of K and M are selected. This patch fixes it.
Merge pull request #3 from ssvb/for-upstream-20140421

Fix problems in 'dram_clk' and 'dram_tpr3' reporting