Extended clock capabilities

Allow the following
```scala
//Standard chisel
val clockA = new Clock(resetA);
//Create a clock domaine with clockA as clock and resetB as reset
val clockA_with_resetB = Clock(clockA,resetB); 
//create clock domaine with current default clock (clk) and resetC
val clk_with_resetC = Clock(null,resetC); 
```
The why is here : https://groups.google.com/forum/#!topic/chisel-users/dW3hLgie9us

I have try to be the less intrusive possible in chisel code to don't add bugs and border effect.
If you find wrong thing in this pull request, give me feed back, and i do a second iteration.

My Todo list is : 
Small fix on reset pin creation chisel's logic, Actualy it's impossible to have a design signal drive a clock domaine's reset, because chisel automaticaly create IO with reset pin, even for module who create the clock domaine. Local reset is a important feature (from my point of view).
Way of fix is : Create reset pin like chisel do, exept for the module who has create the clock domaine .
Fix black boxing clock and reset pin names