vJTAG interface with write select bit and reading from buffer
add sync blocks
add crosssender and crossreceiver for clock domain crossings
ALU
registerfile
add pipline controller
add naive main memory
add decode stage
some of execute stage
add memory stage
modify main memory description
change memory description
change quartus project
add bootloader v1.0
mipsit formatting of .s files
connect mainmem and core. Memory is not inferred by quartus?!?!?!?!?!??!"
fix main memory write description so ram can be correctly inferred
test the memory bits consumption of dual read port memory
add add vjtag interface, needs to be modified
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