VL: add parsing support for assignment patterns, and add consteval support for  system function
Merge remote-tracking branch 'remotes/origin/master' into array
VL: add preliminary support for some new SystemVerilog features:
 - some level of sizing support for unpacked types and assignment patterns
 - support extensional constants '1, '0, 'x, 'z in sizing
 - in always_comb, support variables that are written in some branches
   but not others, by setting them to X when not otherwise set (jared)
Merge master into array

Conflicts:
	books/centaur/vl/mlib/writer.lisp
Merge branch 'array'