tty: cadence: Document DT binding

Add binding documentation for the Cadence UART.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM: zynq: DT: Migrate UART to Cadence binding

The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM: zynq: DT: Add XADC node

Add node for the Xilinx A/D Converter.

Cc: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM: zynq: DT: Add GPIO node

Add node describing Zynq's GPIO controller.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Documentation: devicetree: Adapteva vendor prefix

Cc: Andreas Olofsson <andreas@adapteva.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Documentation: devicetree: Adapteva boards

We're about to add a device tree for the Parallella board.

Cc: Andreas Olofsson <andreas@adapteva.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM: dts: zynq: Add Parallella device tree

This allows to boot the Adapteva Parallella board to serial console.

Cc: Andreas Olofsson <andreas@adapteva.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM: dts: zynq: Add DMAC for Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM: dts: zynq: Add QSPI for Parallella

Prepare SPI0 and SPI1 while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Documentation: devicetree: Fix Xilinx VDMA specification

The specification requires xlnx,data-width, but example and driver use
xlnx,datawidth. Change the specification to match the implementation.

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add VDMA to Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
Documentation: devicetree: Fix ADI AXI SPDIF specification

The specification requires compatible = "adi,axi-spdif-1.00.a" but
driver and example and file name indicate "adi,axi-spdif-tx-1.00.a".
Change the specification to match the implementation.

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add SPDIF for Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: zynq: Add AXI clkgen for Parallella

Signed-off-by: Andreas Färber <afaerber@suse.de>
usb: chipidea: zynq: Add device tree binding information

Document device tree binding information as required by
the ZYNQ USB controller.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
usb: chipidea: Add support for zynq usb host and device controller

Zynq soc uses Chipidea/Synopsys usb IP core(CI13612). This patch adds
necessary glue to allow the chipidea driver to work on zynq soc.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
TEST_ONLY: ARM: dts: zynq: Add USB to Parallella

Awaiting generic Chipidea driver and bindings, this wires up the
proposed v2 of a Zynq-specific driver.

Signed-off-by: Andreas Färber <afaerber@suse.de>
ARM: dts: parallella: Try adding flash

Signed-off-by: Andreas Färber <afaerber@suse.de>