[arch][arm] add support for cortex-a9
[platform][zynq] add quick 'n dirty support for Xilinx Zynq FPGA SoC

-tested against qemu model only at this point
-uart is polled
[platform][zynq] debug uart code tweak

-wait until there's a slot in the fifo before writing
-let the target set the debug uart
[make] fix MODULE_INCLUDES to actually work

-wasn't properly being prefixed with -I and
-wasn't being erased after usage
[platform][zynq] add bootrom header generating python script
[platform][zynq] more zynq tweaks

-Make sure all peripheral irqs are routed to cpu 0
-Implement cortex-a9's private timer
[target][zybo] add initial port to zybo board
[platform][zynq] interrupt driven uart rx
Merge remote-tracking branch 'upstream/master' into x86_64