ArmPkg/DefaultExceptionHandlerLib/Aarch64: Added friendly debug message

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15549 6f19259b-4bc3-4df7-8a09-765794883524
ArmPlatformPkg/Ds5: Added script to profile EDK2 with ARM DSTREAM

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15550 6f19259b-4bc3-4df7-8a09-765794883524
ArmPkg/ArmLib: Drain Write Buffer before DCache maintenance operations.

Cache maintenance operations by Set/Way require that the Write Buffer
be drained before the cache is flushed.  Without that, the flush can
miss the most recent values written as they are still "pipelined".
That has unfortunate consequences, especially where code is being
copied to RAM.
The fix is to add DSB instructions before the affected operations.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15551 6f19259b-4bc3-4df7-8a09-765794883524
ArmPkg: Added new ARM Processor Feature Register definitions

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15552 6f19259b-4bc3-4df7-8a09-765794883524
ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling

See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in
"Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions"
Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524
ArmPkg/AsmMacroIoLib: Add support for ARM Compiler 6.00

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15554 6f19259b-4bc3-4df7-8a09-765794883524
ArmPlatformPkg/ArmVExpressPkg: Set CNTFRQ to 100Mhz for the Fast Models

The timer frequency for the FVP Architectural Timers have been aligned to 100Mhz.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15555 6f19259b-4bc3-4df7-8a09-765794883524
Rename TimeoutInSeconds to Timeout to avoid confusion.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Mike Maslenkin <mihailm@parallels.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15556 6f19259b-4bc3-4df7-8a09-765794883524
MdeModulePkg/NvmExpressDxe: Check if CSTS.RDY is 0 to wait NVMe Host controller disable

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tian, Feng <feng.tian@intel.com>
Reviewed-by: Zeng, Star <star.zeng@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15557 6f19259b-4bc3-4df7-8a09-765794883524
Merge branch 'master' of https://github.com/tianocore/edk2