The commit restores pipelined version of  FPU-100 but now written on Verilog. Actually it isn't completely pipelined because doesn't implement intermediate registers for PC, destination identifier, etc. It is just initial point for further improvement. Opposite to non-piplined version (in fpu folder), the pipelined fpu includes two stage multiplier of fractional parts. The 24x24 bits multiplier is sectioned on 4 multipliers 13x13 (1rst stage) and adder (2nd stage). That allows to synthesis the module with involving a built-in FPGA DSP cells.