omap4: add 4430 ES2.3 support

And default to 4430 ES2.3 for unidentified silicon.

Change-Id: I06b0aa9c5f33af25345996cf9d0c994491093096
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: OMAP4: Fix OMAP4430 ES2.2 identification

There is a break statement missing in the switch statement for ES2.2
devices that will cause ES2.2 devices to be detected as ES2.3.

Change-Id: I0e02ac4303015e843026c7fb3fb5b6f9de0ae058
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: ID: Allow omap443x to enable high performance features dynamically

As the prod id offset is same for 443x and 446x, allow 443x to dynamically
enable high performance features based on si type.
Enable 1.2G/1.5G only if it's high performance device, else fall back to 1G.

Change-Id: I11e3eb7dad54169c9e7d4a88396492c3ec1a2010
Signed-off-by: Girish S G <girishsg@ti.com>
Acked-by: Nishanth M <nm@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: ID: Chip detection for OMAP4470

Add support for detection of the next chip in the OMAP4 family: OMAP4470 ES1.0

Change-Id: I931d3df6e69fdc3ee4a307c204a68fc9b3ff519b
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: ID: Add runtime detection of 4470 1.5Ghz silicon

STD_FUSE_PROD_ID_1[17:16] fuse determines silicon type:
0x1 - Standard performance (1.3 GHz)
0x2 - High performance (1.5 GHz)

Change-Id: I7e37daf1d214d63b35f10fa45952485c59cbc009
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>

Conflicts:
	arch/arm/mach-omap2/board-44xx-identity.c

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: Add 4430 ES2.3 chip is check

4430 ES2.3 chip is check was missed during the merge
phase.

Putting it back in

Change-Id: I94fa2b8f803acb2a13c2f7db4558b2864106d213
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: ID: Remove code duplication during features check

Standard devices is a subset of Performance device.
So Standard features code can be reused for Performance devices.
This removes code duplication.

Also this patch adds 1.3Ghz flag back.
It was removed by mistake during a merge from p-android-omap-3.0 branch.

Change-Id: Ia993fe9e4d90d0557de54ccd1fd5fcb6e16a2782
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: ID: Add high IVA OPPs identification

Some 4460 and 4470 devices support IVA OPPNT and OPPSB.
Add flags to identify this feature.

Change-Id: I6e78d95ca07435c60aae36562a2d9b66fcd1baa4
Signed-off-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4470 LPDDR interface configuration update for 466MHz

Some instability with OMAP4470 when running the DDR at 466MHz is
discovered. This instability is resolved with updated LPDDR settings:

- DLL delay should be set to 461ps:
DDR_PHY_CTRL_1_SHDW[11:4] = 0x37

- Read latency should be set to 0xB:
DDR_PHY_CTRL_1_SHDW[3:0] = 0xB

- Slew Rate should be set to “FASTEST” and Impedance Control to “Drv12”:
CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_SR] = 0
CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_I] = 7
where x=[1-2]

x-loader performs settings all these parameters.
The patch prevents DLL delay to be overridden by the kernel.

Change-Id: Ic7d1733f6c00941f20a2648303a0cb47761ac5df
Signed-off-by: Volodymyr Mieshkov <volodymyr.mieshkov@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: EMIF: code cleanup and clarification

Removed unused fields of emif_regs structure and
functions that initialize or change them.

Also changed few names of emif_regs members
to match register names.

This made the code easier to understand and read
as well as made it a little bit faster

Change-Id: I0485a01b7f03e922b5a2e69bfb03c2ed941fcf3b
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: EMIF: LPDDR interface configuration update

In latest TRMs for OMAP4 family LPDDR recommended
setting have been changed. This patch does
corresponding changes in the code.

Change-Id: Ibd81b8196db74df5a7c3e29788c72a7b3628a22c
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP2: OC Ram according to lastest OZ updates. (466mhz)

Signed-off-by: Dan Trifan <jimsth@gmail.com>
Tweaked RAM timings for better throughtput.

Based on researches by @Pattyboi, @Ziyann and @freshgiammi.
Thanks to @Boype for the first ram timing tweaks.
(RGBandwidth, misc, 1 thread, 20 benchmarks best result wins)

       Stock                     Tweaked

Copy   1249.9 MB/s  -> 1428.7 MB/s -->   14.5 % improvement
Scale  1084.8 MB/s  -> 1304.5 MB/s -->   20.3 % improvement
Add     938.4 MB/s   -> 1223.8 MB/s -->    30.4 % improvement
Triad   923.0 MB/s   ->  1191,7 MB/s -->   29.1 % improvement

Signed-off-by: Gianmarco Rengucci <rengucci.gianmarco@gmail.com>

Signed-off-by: Dan Trifan <jimsth@gmail.com>
omap2: enable some erratas

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
init: debug: bye bye

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
writeback: Fix occasional slow sync(1)

In case when system contains no dirty pages, wakeup_flusher_threads()
will submit WB_SYNC_NONE writeback for 0 pages so wb_writeback() exits
immediately without doing anything. Thus sync(1) will write all the
dirty inodes from a WB_SYNC_ALL writeback pass which is slow.

Fix the problem by using get_nr_dirty_pages() in
wakeup_flusher_threads() instead of calculating number of dirty pages
manually. That function also takes number of dirty inodes into account.

CC: stable@vger.kernel.org
Reported-by: Paul Taysom <taysom@chromium.org>
Signed-off-by: Jan Kara <jack@suse.cz>
Signed-off-by: Cristoforo Cataldo <cristoforo.cataldo@gmail.com>
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
i think this needs applied as well

Signed-off-by: Dan Trifan <jimsth@gmail.com>
mm/ksm: engage deferred timer by default

Signed-off-by: Paul Reioux <reioux@gmail.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: 6995/2: mm: remove unnecessary cache flush on v6 copypage

Originally introduced to maintain coherency between icache and dcache
in v6 nonaliasing mode. This is now handled by __sync_icache_dcache since
c0177800, therefore unnecessary in this function.

Signed-off-by: Heechul Yun <heechul@illinois.edu>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: mm: Add v7_flush_dcache_by_level() API.

On ARMv7 based SOC with an integrated L2 cache, there is a need
to have a flush API to operate on each cache level. In few low power
modes, L2 cache is retained where as L1 is lost. The current
v7_flush_dcache_all(), flushes all the levels and
it would be quite expensive.

So introduce v7_flush_dcache_by_level() API which takes a
parameter (cache level), and flush only on that level.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Dan Trifan <jimsth@gmail.com>