x86: Avoid crashes under QEMU due to missing DMAR units

Make sure we do not crash in the hypervisor when adding or removing
cells with PCI devices under QEMU. These hacks will be removed once
emulated VT-d is available.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
doc: update README

The README had one line where the old jailhouse syntax was still used,
update it to the new syntax.

Signed-off-by: Henning Schild <henning.schild@siemens.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
TODO: Update and detail list

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
core: Provide details on PCI MMCONFIG access violations

Support the user in parsing MMCONFIG write rejections by decoding the
BDF and providing the accesses register number.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Further improve EPT error reporting

Avoid double error reporting in vmx_handle_ept_violation if an access
handler already did this. Also correct the access direction message, it
was inverted.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Report APIC access on MMIO parsing error

This ensures that the context of the MMIO access is clear.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Report details on string/REP-prefixed PIO access

Do not just silently return an error code without telling the user what
kind of vmexit handling just failed.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
core: Drop root_cell argument from arch_init_early/late

root_cell is already globally available, no need to pass it around.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
core/configs: Change IRQ line access control modeling

Change the configuration file to manage access to IRQ lines at IRQ chip
level. Each IRQ chip config entry consists of a unique identifier,
typically the chip's MMIO address, and a bitmap controlling access to
individual IRQs lines of that chip. This will simplify access control
checks to IRQ chips.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Add support for Mod 1 to MMIO parser

The only difference to Mod 2 is the length of the displacement: 1
instead of 4 bytes.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
x86: Add support for IOAPIC access control

This adds basic access control to the IOAPIC. Based on the IRQ chip
configuration, we permit or deny writing to redirection table entries.
This needs to be integrated with interrupt remapping later on.

We furthermore allow reads from other valid IOAPIC registers but deny
any other write accesses.

EOI writing is currently passed through. This will have to be
virtualized as well when interrupt remapping is added.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
configs: Make use of IOAPIC moderation

Remove the IOAPIC page from the memory regions and add the IOAPIC as
irqchip instead.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>