i965: Make INTEL_DEBUG=mip print out whether HiZ is enabled.

We only enable HiZ for miplevels which are aligned on 8x4 blocks.  When
debugging HiZ failures, it's useful to know whether a particular
miplevel is using HiZ or not.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.

Like on Haswell, we need to use 8x4 aligned rectangle primitives for
hierarchical depth buffer resolves and depth clears.  See the comments
in brw_blorp.cpp's brw_hiz_op_params() constructor.  (The Broadwell
documentation confirms that this is still necessary.)

This patch makes the Broadwell code follow the same behavior as Chad and
Jordan's Gen7 BLORP code.  Based on a patch by Topi Pohjolainen.

This fixes es3conform's framebuffer_blit_functionality_scissor_blit
test, with no Piglit regressions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
nv50: make sure to mark first scissor dirty after blit

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
tgsi/ureg: add ureg_UARL shortcut
mesa,gallium: API settings / rasterization rules
gallium-drivers: use API settings / rasterization rules
nv50,nvc0: handle TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
nv50,nvc0: handle NULL vertex elements without fallback
nv50/ir/tgsi: implement TGSI_OPCODE_NRM,DP2A

Used by d3d9 st.
nv50: don't emit buffer for skipped vertex elements

Grr, should forbid that and insert dummy elements in nine.
nvc0: avoid fault in get_query_result if there was no begin_query
gallium: add PIPE_CAP_DEVICE_MEMORY_SIZE
softpipe: handle PIPE_CAP_DEVICE_MEMORY_SIZE

Because the compile warning is annoying.
r600g: handle PIPE_CAP_DEVICE_MEMORY_SIZE
winsys/sw/wrapper: hook up is_displaytarget_format_supported

Looks like no one's using this thing.
gallium/draw: support hack to disable clipping
nv50: support for hackish viewport bypass
nv50,nvc0: d3d9 requires transfer stride to be aligned to 4
gallium: add blending to pipe blit
nvc0: use blending to pipe blit