ARM64: add support for cache management instructions (Valgrind side):
  dc cvau, regX
  ic ivau, regX
  mrs regX, ctr_el0
Fixes #333228 and #333230.



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13931 a5019735-40e9-0310-863c-91ae7b9d1cf9
VG_(invalidate_icache) for ARM64: fix incorrect computation of cache
line sizes.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13932 a5019735-40e9-0310-863c-91ae7b9d1cf9
Update aarch64 fixes.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13933 a5019735-40e9-0310-863c-91ae7b9d1cf9
Renaming only (no functional change): rename IR artefacts to do 
with i-cache invalidation to be more consistent with new d-cache
flushing functionality, so as to track changes in Vex r2852:
  Ijk_TInval          -> Ijk_InvalICache
  TISTART             -> CMSTART (CM == "Cache Management")
  TILEN               -> CMLEN
  VEX_TRC_JMP_TINVAL  -> VEX_TRC_JMP_INVALICACHE



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13934 a5019735-40e9-0310-863c-91ae7b9d1cf9