Linux 3.4.87

Signed-off-by: LaboDJ <jacopolabardi@gmail.com>
crypto: msm: check NULL pointer in _qcrypto_setkey_des()

add NULL pointer check before des_ekey()

Change-Id: I57c40b82fc5141c1666c3fd493b43e962f0d1ae9
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: Add support for aead

Add support for aead mode algorithms (simultaneous auth
and cipher operations)

Change-Id: I22cc530f8fe822504649cb3c60030a729e1305c2
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
crypto: msm: Fix Uninitialized flags

Due to uninitialized "flags" field in the request structure,
incorrect choices are made in the qce driver layer with
regards to setting crypto hardware registers.

Initializing the flags fixes this incorrect setting of the
registers.

Change-Id: Ic40319ea5e15e66cbafd28f727a9bcc6ea41b1ca
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
crypto: msm: check potential integer overflow on AEAD req length

According to the specification of AEAD, AEAD request cryptlen is
not a Fixed maximum and assoclen is also same. This could lead to
potential integer overflow, thus allocating less memory. So we
need to check potential integer overflow on AEAD request length.

Change-Id: I58a0c5e1a6e890bad30f7865e96b7db46337158c
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: Use scnprintf() instead of snprintf()

snprintf can return more than the size of buffer, which is not
expected here, obviously. Use scnprintf instead.

Change-Id: I3b97a016df910728dfef5a0914ab8ad67c68e39c
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
crypto: msm: Fix null pointer exception in qcrypto_count_sg()

Fixes null pointer exception in count scatter gather function. Scatter
gather list pointer become NULL if the sg pointer reaches last but one
node, which results in NULL pointer exception.

Change-Id: I634baf30074e6e53ffa22635565da54e9ae43150
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
crypto: msm: multiple qce50 support

In some platforms such as fsm9900, multiple instances of qce50 hw
may be supported.  Each qce50 HW has an ndp-bam. Each qce50 HW
can support multiple instances of qce_dev platform device.
Each qce_dev has its own configured pipe set and associated qce50 HW,
defined by crypto-base and bam-pipe-pair fields in the device tree files.
This patch based on io address, it decides to create a new qce50 hw
instance or use the existing known instance at device probe time.

Furthermore, this patch does iomap for only once for each HW BAM instance
to avoid issue with bam driver. If modprobe, and rmmod of qcedev,
and qcrypto are not in first in last out order, kernel may crash in
bam driver in the last rmmod.
This saves virtual space for IO if multiple instances of qcedev
share the same instance of HW BAM.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: Fix issues related to non-zero byteoffset input

Fix buffer overflow for a non-zero byteoffset value.

Also fixes memory leak issue by adding data_len check in check_params.
One of the scenarios data_len can be less than byteoffset which results
in memory leak with huge data length, which might cause the kernel panic.

Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: Remove invalid check in qcedev driver

Unsigned int variable is compared for < 0, which is an invalid if
condition. This patch removes the check.

Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: qce50 ota crypto support

Kasumi/snow-3g f8/f9 are defined by 3gpp, as the algorithms for
UMTS, and LTE for over the air ciphering and integrity. The
algorithms are supported by crypto 5 hardware. This patch
enables qce50 driver to provide Kasumi/snow-3g f8/f9
ciphering and integrity services.

Acked-by: hemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: Handle error case

Release memory and disable clk when sps_init fails.

Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: Add support for setting XTS data unit size

Based on the context flags set by client, set XTS_DU_SIZE
register to sector size of 1KB, or the actual total length
of the packet.

Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: optimize ce bandwith scaling

Encryption processing at qcrypto driver includes three main steps:
set ce high bandwidth and enable ce clock in cra_init, then send
encrytion request, and at last set ce low bandwidth and disable
clock in cra_exit. This process is fine for the use case where
there are lots of requests between cra_init and cra_exit, but will
introduce large overhead for mmc layer disk encryption as it calls
cra_init, queue request and cra_exit for every encryption request.

It is not necessary to set low bandwidth and disable clock for every
encrypt request when it is completed. So we delay these scaling down
tasks for a while, and just scale down the last request when timer
expires so as to amortize and decrease the overhead.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: fix issues in ce clock disable processing

In the situation of more than one requests, the ce clock may get
errorneously disabled even when there are active requests. The
scaling operation is then modified to fix the problem and ensure
all requests are completed when disable the clock. We also clean
up the related codes.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: multiple qcrypto support

This patch provides support for multiple qcrypto devices
with the qcrypto driver.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: fix hmac hashing issues with various key size

hmac-sha1 and hamc-sha256 have variable mac key up to a block size.
If user provides a key that is less than the block size, the
key should be padded with zero to the block size before it is
given to the hw.

This padding was not done properly in the driver.
When switch engine between ahash hmac(sha1), hmac(sha256),
and ipsec, problem may happen. ipsec takes 20 bytes of key.
The generated digested data is wrong, even though everything looks
fine from driver. ipsec may fail.

Furthermore, this patch cleanup the driver to do proper setup of
hardware to use hw key or pipe key.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: fix hmac ahashing issues with simultaneous multiple requests.

 This patch fixes two issues. One issue is to do with simultaneous requests
 of a ahash tfm. The other issue is to do with ahash import, and export
 functions.

 Agent issues chain of requests in sequence of init, followed
 by multiple updates, and final to the crypto driver for the hashing of a
 buffer. Each request can be asynchrounous. After a request is complete,
 the next one in the sequence is issued.

 Multiple simultaneous async requests can be issued to the driver
 for the same tfm if they are for independent hashing.

 In the driver, the state variables such as trailing buffer, first
 block, last block are maintained in the driver. The
 state variables are maintained in the request context, instead of
 tfm context. Otherwise, simultaneous async requests can
 confuse each other. This patch moves those variables out of
 tfm context to request context to fix this issue.

 Agent above the driver can import/export ahash state of a request. This
 patch fixes a few issues in the driver to support import/export.
 First issue, the byte count returned from hw for hmac has 64 bytes of
 padding on the first request to the hardware. In the import/export this
 special case needs to be accomodated.

 The 2nd issue is the state buffer is only updated after hardware operation
 complete. For the first, data being accumulated in the trailing buffer,
 and if request has not ever issued to the hw, when import function comes,
 the trailing data needs to be exported. This patch uses trailing
 buffer directly as state buffer variable for import and export.
 The context update functions after hareware request complete are not
 necessary and they are removed. The last issue is to do with state
 variable count. It was not initialized. That may cause hashing generated
 wrong  digest after export and import.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: add pm wakeup support for qcrypto driver

Add support for holding system from suspending while an operation
is in progress (when clks are enabled).  This is done by invoking
pm_stay_awake before enabling clks (when a crypto operation is
initiated) and invoking pm_relax when crypto operation is done.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
crypto: msm: Fix key length setting

Hardcoding key length to a constant value results in overwriting
command element information in the command descriptor beyond what
is allocate for the key information in the command element list.
This results in corruption of the command list in the case where
command descriptors are used for configuring crypto registers and
needlessly writing to key registers that are not relevant to the
operation (when writing to registers directly), and thus leads to
crypto operation failures. Fix is to use the key length based on
what is requested by the client.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>