Tidy GigE phy init code
Use LEDs for debug output from GigE PHYs
Merge branch 'master' of github.com:jboone/daisho

Conflicts (strange, because they didn't actually conflict):
	sw/fpga/targets/gige/gige_top.v
	sw/fpga/targets/gige/phy_init.v
Add a quick serial->pcap tool for Black Hat demo
Fix copyright notice
usb2/usb3: initial usb3 phy support, link training, changes to usb2 to allow usb3 testing
usb2/usb3: default FSM states, unbroken 2.0, prelim rx descrambling 3.0
usb3: del redundant file
Add support for pipes
Black Hat demos
usb3: improved TS1/TS2 detection efficiency
usb3: preliminary TX scrambling
Merge pull request #2 from jboone/master

GigE demo code from Black Hat 2013 -- UART output only. - merged from Jared's repository.
usb3: continue link layer development
usb3: continued link development
usb3: continue link layer
usb3: link supporting additions
usb3: start protocol layer
Update rs232 top module to match changes to USB core.
usb2: fixed stuck reset in ulpi