some work
add snapshotting
Update docs
Make tests pass
refactor in progress
WIP
fix some stuff
update tests, fix more bugs
remove the extra gitignore line from who knows where
Don't emit empty "_chisel_temps_" VCD module

Jim Lawson suggested this fix, but for some reason I seem to have
dropped the ball and not actually committed it...
Emit the correct MUL constant widths

It turns out the MUL width inference rules are different than I
thought.  If we have "A <- B + C", we need the width of A to be the
sum of the widths of B and C -- I thought it was that B and C had the
same width and A was double their width.

This adds some extra logic to make export constants of the correct
width to Flo files.  Like before, it's a bit of a mess and fails when
there's two constants, but I think it's good enough for now...
Fix VCD dumps

WIRE__prev was not getting set during the first cycle's VCD dump,
which can result in inconsistent VCD dumps.  Essentially the idea is
that if your circuit has a wire that starts as non-zero and becomes
zero after the first cycle, the VCD dump will never reflect this
change.
use the mem_peek command instead of wire_peek for Mem peeks
remove counter_shadow & pseudoMuxes
make only unconsumed top level outputs outs
merge
Avoid redundantly obtaining stack traces

They impose a surprisingly significant runtime penalty.
Remove vestigial reserved keyword support
Remove vestigial saveWidthWarnings variable

We should deprecate --Wwidth, since it does nothing.
Remove vestigial options