stm32: exti: Define all irqs in common header.

There's more exti lines on many more devices now. F0 and F3 have extras, as did
L1 and L0.  There's no real reason not to have higher order EXTI definitions
defined at the top level, and it reduces the number of files to merge together
to find all definitions for the bigger devices.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>

Fixes #338
stm32/spi: Replace all SPIx_I2S_BASE with SPIx_BASE

Latest versions of all reference manuals refer to the address as SPIx_BASE, and
simply name some of the individual registers as SPI_I2SXXXX.  Likewise, the
interrupts are simply SPIx, not SPIx/I2Sx.  Rather than hacking more duplicates
into the F0 and L0 parts where this was turning up, remove the pointless _I2S_
from SPI2/SPI3 and make it all consistent

Compile tested only, with the examples collection.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>

Fixes #331
Fixes #347
stm32: Add timers 9-17.  This should support all F0, F1, and F2 products
stm32: i2c: actually keep bit 14 set as per datasheet.

Old code did three writes, new way actually seems to follow datasheet
properly.
init: call pre_main before C++ constructors

This moves the platform specific initialization function pre_main
in front of C++ constructors. This is especially necessary for
platforms which need to setup the stack pointer (pre_main itself
is inline, hence no stack needed for this function).
stm32: gpio_toggle: ensure correct state of non-toggled pins.
stm32: common: fix missing SPI_I2S_BASE rename regression

Fix regresion from 5d4437fe43aa68a28611e9a0aecc712833230304 where
somehow not all occurrences were replaced.  I could swear it all
compiled when I was working on it :(

Reported-by: Trevor Woerner <trevor.woerner@linaro.org>
[f4] Added a 25mhz clock
Renamed README to README.md to be recognized as Markdown by GitHub
Markdowned README.md
vf6xx: initial add of Vybrid VF6xx support

Freescale Vybrid is a familiy of ARM SoC, wheras the VF6xx models
have two cores in one SoC, a Cortex-A5 and a Cortex-M4. This adds
initial support for the Cortex-M4 in the libopencm3 library.

By using two different ram areas (pc_ram and ps_ram) the user can
put the code in a RAM area bounded to the code bus. The data can
be stored in the data area. However, currently the initial values
of for the variables in the data section are stored in the code
section and copied to the ram section by the initialization code
(like it's copied from ROM to RAM on microcontrollers).
vf6xx: set vector table to memory

Set Vector Table Offset to memory location of our vector table.
Since we put the whole programm including the vector table into
memory, we need to make use of the Cortex-M4 system control block
Vector Table Offset Register (VTOR).
vf6xx: initial memorymap and clock control module

Add initial memorymap for Vybrid VF6xx module. Also add the clock
control module which allows to control system clocks and enable
clocks of individual pheripherials.
vf6xx: doc: initial commit

Add documentation Makefile and DoxygenLayout for Freescale Vybrid
VF6xx support.
vf6xx: enable floating-point coprocessor
vf6xx: calculate core clocks

Extend the clock controller module with a function to calculate
core clocks from the current registers settings. On Vybrid, we
assume that the core clocks are setup by the main operating system
running on the Cortex-A5. Nevertheless we need to know their actual
values in order to calculate other clocks or baud rates.

Verified on a Colibri VF61, which calculates following values:
ccm_core_clk: 500210526
ccm_platform_bus_clk: 166736842
ccm_ipg_bus_clk: 83368421
vf6xx: add UART support

This adds UART support for Vybrid VF6xx. Baud rate is calculated
from IPG clock, which need to be initialized by using the
ccm_calculate_clocks functions. Also clock need to be gated using
the ccm_clock_gate_enable function. Tested with an unitialized
UART with a baud rate of 115200.
vf6xx: initial GPIO support

This adds GPIO module support. GPIO can be controlled using the GPIO
number as stated in the reference manual, similar to Linux. Also
32-bit access to whole ports is possible. Reading a GPIO is possible
without muxing the pad as GPIO, however writing a GPIO needs the pad
to be muxed as GPIO.
vf6xx: add I/O mux controller

Add I/O mux controller which is required to mux pins according to
their used function. For all pads, the alternative function 0 is
GPIO. For different pin mux function refer to the reference manual.
[stm32l0] Initial support for STM32L0 architecture, Add GPIO peripheral