hdl/ip_cores/dsp-cores: update submodule reference
hdl/*/*/wb_fmc130m_4ch/*: add optional register link module

As the design gets bigger, it may be difficult to
meet timing constraints for all Wishbone paths, specially
with nested crossbars. This patch adds a generic option
to enable an additional regsiter on the Wishbone path to
ease timing.
hdl/modules/*/*: update wb_fmc130m_4ch module declaration
hdl/modules/*/reset_synch/*: add MAX_FANOUT attribute

Add Xilinx MAX_FANOUT attribute to try to reduce
the reset fanout