verilog: Fix scope for nested constructs

I don't know if such nesting is valid in Verilog, but the parser would duplicate some scope elements with deep nesting.

This had dramatic implication when parsing invalid input like e.g. *Test/jsFunc_tutorial.js* as it lead to largely nested scopes getting duplicated, resulting in overly large output and memory usage.

This fix mitigates the issue as the scope is not duplicated anymore and the growth with such invalid input is now linear and not exponential anymore.

Parsing of *Test/jsFunc_tutorial.js* is now virtually instantaneous, uses about 2M of memory and results in a 7.7K file, where it used to take forever and use several gigabytes of memory and disk space (I don't have numbers because it did not finish in several minutes yet already used more than 2G of memory and 1.1G of disk space).

----

I don't know Verilog so I can't tell whether the test case is correct or not (I doubt it strictly is), but anyway I can't believe the duplicate scope is correct.

In practice, this fixes `make -f testing.mak FUZZ_LANGUAGE=Verilog fuzz`.