clocksource: arm_global_timer: Only check for unusable timer on A9

The check for a usable global timer in the probe code does not enquire
which CPU we are currently running on. This can cause the driver to
incorrectly assume we have an unusable global timer if we are running
on a CPU other than A9.

Before checking the CPU revision, ensure we are running on an A9 CPU.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
documentaion: DT: allow a A5 compatible string in global timer

The global timer is present on the Cortex A5. Add a compatibility
string to the DT binding to allow a Cortex A5 global timer.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
dts: ca5: add the global timer for the A5

The Cortex A5 contains a global timer: add the appropriate device tree
node.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform

The Cortex A5 now contains bindings for the global timer
driver. Ensure that the driver is built with a vexpress platform.

Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
clocksource: efm32: use $vendor,$device scheme for compatible string

Wolfram Sang pointed out that "efm32,$device" is non-standard. So use the
common scheme and prefix device with "efm32-". The old compatible string
is left in place until arch/arm/boot/dts/efm32* is fixed.

Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Merge branch 'clockevents/cmt-mtu2-tmu-cleanups' into clockevents/3.16

This patch set cleans up the Renesas CMT and TMU drivers in preparation for DT
support.

The first 35 patches are a bunch of necessary cleanups that reorganize the CMT
and TMU drivers, their platform data, and the memory, interrupt and clock
resources they expect. As a result the drivers accept a new platform data
model close to the hardware with supports for all the timer channels using a
single device.

The next 13 patches (36/52 to 48/52) move all CMT and TMU platforms from the
old to the new platform data model. Patches 49/52 to 52/52 then drop support
for the old model and perform one more cleanup.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
clocksource: sun5i: Add support for reset controller

The Allwinner A31 that uses this timer has the timer IP asserted in reset.
Add an optional reset property to the DT, and deassert the timer from reset if
it's there.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
ARM: sun6i: a31: Add support for the High Speed Timers

The Allwinner A31 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.

Now that we have a driver to support it, we can enable them in the
device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
sched_clock: Remove deprecated setup_sched_clock() API

Remove the 32-bit only setup_sched_clock() API now that all users
have been converted to the 64-bit friendly sched_clock_register().

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
genirq: Sanitize spurious interrupt detection of threaded irqs

Till reported that the spurious interrupt detection of threaded
interrupts is broken in two ways:

- note_interrupt() is called for each action thread of a shared
  interrupt line. That's wrong as we are only interested whether none
  of the device drivers felt responsible for the interrupt, but by
  calling multiple times for a single interrupt line we account
  IRQ_NONE even if one of the drivers felt responsible.

- note_interrupt() when called from the thread handler is not
  serialized. That leaves the members of irq_desc which are used for
  the spurious detection unprotected.

To solve this we need to defer the spurious detection of a threaded
interrupt to the next hardware interrupt context where we have
implicit serialization.

If note_interrupt is called with action_ret == IRQ_WAKE_THREAD, we
check whether the previous interrupt requested a deferred check. If
not, we request a deferred check for the next hardware interrupt and
return. 

If set, we check whether one of the interrupt threads signaled
success. Depending on this information we feed the result into the
spurious detector.

If one primary handler of a shared interrupt returns IRQ_HANDLED we
disable the deferred check of irq threads on the same line, as we have
found at least one device driver who cared.

Reported-by: Till Straumann <strauman@slac.stanford.edu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Austin Schuh <austin@peloton-tech.com>
Cc: Oliver Hartkopp <socketcan@hartkopp.net>
Cc: Wolfgang Grandegger <wg@grandegger.com>
Cc: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Cc: Marc Kleine-Budde <mkl@pengutronix.de>
Cc: linux-can@vger.kernel.org
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/alpine.LFD.2.02.1303071450130.22263@ionos
timer_stats/doc: Fix /proc/timer_stats documentation

Documentation/timers/timer_stats.txt claims:

 "The readout of /proc/timer_stats automatically disables sampling. The sampled
  information is kept until a new sample period is started. This allows multiple
  readouts."

Some simple testing shows that reading from /proc/timer_stats
does not disable sampling. Looking back over past source code,
it appears that it never did.

Signed-off-by: Michael Kerrisk <mtk.manpages@gmail.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Link: http://lkml.kernel.org/r/53636FB6.9060407@gmail.com
[ Small tidyup of the changelog. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Merge tag 'irqchip-mvebu-3.16' of git://git.infradead.org/linux-mvebu into irq/core

irqchip mvebu changes for v3.16 from Jason Cooper:
* orion: reverse irq handling priority
* armada-370-xp: do set_smp_cross_call in the driver
* armada-370-xp use cpu notifier to init secondary cpus

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
ntp: Convert simple_strtol to kstrtol

Replace obsolete function simple_strtol w/ kstrtol

Inspired-By: Andrew Morton <akpm@linux-foundation.org>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Fabian Frederick <fabf@skynet.be>
[jstultz: Tweak commit message]
Signed-off-by: John Stultz <john.stultz@linaro.org>
ntp: Make is_error_status() use its argument

is_error_status() is an inline function always called with the
global time_status as an argument, so there's zero functional
difference with this change, but the non-CONFIG_NTP_PPS version
uses the passed-in argument, while the CONFIG_NTP_PPS one ignores
its argument and uses the global.

Looks like is_error_status was refactored out, but someone forgot
to change the logic to check the local argument value.

Thus this patch makes it use the argument always; shorter variable
names are good.

Signed-off-by: George Spelvin <linux@horizon.com>
[jstultz: Tweaked commit message]
Signed-off-by: John Stultz <john.stultz@linaro.org>
Merge branches 'linus' and 'irq/urgent' into irq/core

Reason: Get the upstream and urgent fixes before applying more complex
changes.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arm: iop13xx: Use sparse irqs for MSI

No need for a private allocator. The core code handles it
already. 

Allocate the non MSI irqs right at boot time via machine_desc->nr_irqs
and let the sparse core handle the MSI space.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Grant Likely <grant.likely@linaro.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/20140507154333.809210026@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
mips: Kill pointless destroy_irq()

Copy and paste leftovers with no functionality at all.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Grant Likely <grant.likely@linaro.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Link: http://lkml.kernel.org/r/20140507154334.008113902@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
genirq: Provide generic hwirq allocation facility

Not really the solution to the problem, but at least it confines the
mess in the core code and allows to get rid of the create/destroy_irq
variants from hell, i.e. 3 implementations with different semantics
plus the x86 specific variants __create_irqs and create_irq_nr
which have been invented in another circle of hell.

x86 : x86 should be converted to irq domains and I'm deliberately
      making it impossible to do the multi-vector MSI support by
      adding more crap to the current mess. It's not that hard to do
      and I'm really tired of the trainwrecks which have been invented
      by baindaid engineering so far. Any attempt to do multi-vector
      MSI or ioapic hotplug without converting to irq domains is NAKed
      hereby.

tile: Might use irq domains as well, but it has a very limited
      interrupt space, so handling it via this functionality might be
      the right thing to do even in the long run.

ia64: That's an hopeless case, as I doubt that anyone has the stomach
      to rewrite the homebrewn dynamic allocation facilities. I stared
      at it for a couple of hours and gave up. The create/destroy_irq
      mess could be made private to itanic right away if there
      wouldn't be the iommu/dmar driver being shared with x86. So to
      do that I'm going to add a separate ia64 specific implementation
      later in order not to deep-six itanic right away.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Grant Likely <grant.likely@linaro.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: x86@kernel.org
Link: http://lkml.kernel.org/r/20140507154334.208629358@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
x86: Implement arch_setup/teardown_hwirq()

This is just a cleanup to get rid of the create/destroy_irq variants
which were designed in hell.

The long term solution for x86 is to switch over to irq domains and
cleanup the whole vector allocation mess.

The generic irq_alloc_hwirqs() interface deliberately prevents
multi-MSI vector allocation to further enforce the irq domain
conversion (aside of the desire to support ioapic hotplug).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Grant Likely <grant.likely@linaro.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: x86@kernel.org
Link: http://lkml.kernel.org/r/20140507154334.482904047@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
x86: irq_remapping: Use irq_alloc/free_hwirq()

The create_irq variants are going away. Use the new interface. The
core and arch code already excludes the gsi interrupts from the
allocation, so no functional change.

This does not replace the requirement to move x86 to irq domains, but
it limits the mess to some degree.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Grant Likely <grant.likely@linaro.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Acked-by: Joerg Roedel <joro@8bytes.org>
Cc: x86@kernel.org
Cc: iommu@lists.linux-foundation.org
Link: http://lkml.kernel.org/r/20140507154334.741805075@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>