NetCase::synth_async gets a better handle on partly used inputs

Better handle the case where the output for some pins comes from
an earlier assignment. This allows for multiple ways to specify
default outputs for some cases: the default: case and pre-assignment.
Fix some weird lint found by clang

Small stuff, no behavior change expected.
Pick some low-hanging const fruit

Makes more of the code const-correct; there are still plenty of difficult-to-fix const problems left.
No behavior change expected.
Fix for GitHub issue #28 - Insufficient string escaping in vvp script.

" characters in strings must be escaped when the compiler writes a
quoted string to a vvp script. This patch fixes up a few places where
this wasn't being done.
Don't lie to the c++ about some pointer alignment

Second try cleaning up cast-alignment problems surrounding need_result_buf().
Clang gave a bunch of warnings like
vvp/vpi_const.cc:196:34: warning: cast from 'char *' to 'p_vpi_vecval' (aka 't_vpi_vecval *') increases required alignment from 1 to 4 [-Wcast-align]

This version is verbose and changes the prototype for need_result_buf().
But it is semantically (c++) correct, and makes need_result_buf() feel like malloc().
Tie up simple loose ends for need_result_buf()

vvp/ is now free of -Wcast-align errors
Update fstapi files to latest ones from GTKWave
Update fstapi.c to latest from GTKWavE (remove some compile warnings)
A bit select is not the same as selecting part of a packed array

When adding the ability to select part of a multi-dimensional packed
array the sign and size information for a true bit select was broken.
Add support for a single argument $urandom_range() call
Handle special case of missing condit inputs.

It shouldn't be possible, but sometimes is, that a NetCondit is
missing input nets during async synthesis. Handle this by generating
a place-holder net and printing a warning.
Add synthesis support for casez statements.

This generates an EQZ LPM device that carries the case-z-ness to
the code generator.

Also add to the vvp code generator support for the EQZ device so
that the synthesis results can be simulated.

Account for the wildcard devices in the sizer.
case/x/z synthesis with constant case expression.

If the case expression is constant, then the guards probably are
not, and the synthesis should be handled differently.
Spell, etc. fixes
Merge branch 'master' into x-sizer5
Basic DFF asynchronous set/reset synthesis support.
More flexible synthesis of DFF with asynchronous set/reset.
Fix argument ordering for synthesized casez compare.
Merge https://github.com/steveicarus/iverilog

see if the d-flip-flops show up after synthesis now...
another verilog file

This time a PCI target, which crashes the synthesizer...