target-mips: add MAAR, MAARI register

The MAAR register is a read/write register included in Release 5
of the architecture that defines the accessibility attributes of
physical address regions. In particular, MAAR defines whether an
instruction fetch or data load can speculatively access a memory
region within the physical address bounds specified by MAAR.

As QEMU doesn't do speculative access, hence this patch only
provides ability to access the registers.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
target-mips: update mips32r5-generic for MAAR

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
target-mips: add HTW registers

Add PWBase, PWField, PWSize and PWCtl registers.
These are required for the Hardware Table Walker.
PWCtl.PWEn is always 0 as Hardware Table Walker is not implemented.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
target-mips: update mips32r5-generic for HTW

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Merge pull request #6 from yongbok/p5600-mips32r5-PRIP3

MAAR and HTW CP0 registers