compiler/arm/call: Define VOP XEP-ALLOCATE-FRAME.

  * Based on the PPC version, with various ARM-specific cleverness.

  * Calculating reg_CODE is done as a short instruction sequence,
and uses PC-relative addressing and the header value for the
simple-fun object, rather than a displacement.

  * Dealing with the number stack is disabled, as it's not yet
required.
build-order.lisp-expr: Disable (for now) building VM-IR2TRAN on ARM.

  * Too much trouble to make work right now, but will clearly have
to be made to work fairly soon.
compiler/arm/pred: Define the BRANCH VOP.

  * Copied verbatim (even the instruction name is the same!) from
the PPC backend.
compiler/arm/pred: Implement VOP BRANCH-IF and related support routine.

  * This is a copy, verbatim except for an added FIXME-comment, of
the PPC implementation of VOP BRANCH-IF and vm-support-routine
CONVERT-CONDITIONAL-MOVE-P.  They are intended for the most basic
of predicated code, which ARM should be able to handle quite well,
but will have to be attended to as a future optimization rather
than something critical for getting things running in the first
place.
compiler-ir2tran: Re-enable some "important bits" on ARM.

  * We now have VOPs BRANCH and BRANCH-IF, which allows us to
re-enable the bits that refer to these VOPs.
make-host-1.lisp: Suppress one of the before-xc tests on ARM.

  * The test file in question depends on part of the backend that
is not yet implemented.
compiler/generic/genesis: Don't export FLOAT-* constants on ARM.

  * Some four related constants are normally exported by genesis,
but we have yet to define them on ARM.  Suppress their export.
compiler/arm/vm: Support routine COMBINATION-IMPLEMENTATION-STYLE

  * This is some sort of hook for machine-specific optimization,
when the backend can provide better optimization for certain
functions when it has access to the high-level form rather than
the lower-level forms that the front-end normally makes of them.

  * The MIPS backend has a do-nothing implementation, so crib from
that for now.
compiler/arm/vm: More register renaming.

  * Swipe a few registers for OCFP, LRA, NARGS, and NFP.  The "old
current frame pointer", "lisp return address", "number of
arguments" and "number frame pointer", respectively.  OCFP, LRA,
and NARGS are all calling-convention-related, and only LRA must
be boxed (the others can be either, they'll always appear as
FIXNUM values).  NFP likewise can be either, but is only used
within a function, not really over a function-call boundary.
compiler/arm: A bunch of funcall-related VM support.

  * Copied from the PPC backend.  Verbatim.  It's pretty much the
same for any backend, except the x86oids anyway.
compiler/ir2tran: Fix ARM disablement of IR2-CONVERT optimizers.

  * Instead of outright removing the optimizers, leave them in
with their bodies replaced with ERROR forms.  This way we'll know
what's going on when they're supposed to be triggered, rather than
have to try and figure it out from a wierd trace file or other
downstream error.
compiler/generic/genesis: ARM wants boxed FDEFN raw-addr values.

  * Like SPARC, the ARM processors have the ability to apply an
arbitrary displacement in the jump instruction.  In the ARM case,
it is actually literally ANY ALU operation with the program
counter as a destination.  We could shift or rotate some register
left or right, add the result to a second register, and load the
result into the program counter in a single instruction.  We're
going to take advantage of this in our call sequence, but this
means fixing up the COLD-FSET handling in genesis to match the
SPARC version.
compiler/arm/call: Fix reg_CODE calculation in XEP-ALLOCATE-FRAME.

  * Got the displacement backwards.  Oops.
compiler/arm/call: Fix two bugs in RETURN-SINGLE.

  * When using the MSR instruction, the field mask is supposed to
be encoded by CPSR or SPSR, not passed "raw".

  * It turns out that the CPU doesn't like negative immediate
values.  Replace ADD with SUB and switch things around to get the
correct result from a positive immediate value.
compiler/arm/insts: Mask encoded shifter_operands properly.

  * In two places, neglected to mask the low part of an encoded
shifter_operand, which causes problems when the high part contains
a set bit.

  * Fix, by masking the field down with LDB.
compiler/arm/insts: Fix status-register field specification encoding.

  * Since the common use-case for status register fields is going
to be keyword symbols, we should be checking for upper-case
letters, not lower-case letters.  Saves us from having :|f| in our
source code instead of :f.
compiler/arm/move: Fix bug with LOAD-IMMEDIATE for FIXNUM values.

  * Such a simple little thing, forgetting to call FIXNUMIZE on
the value leads to trying to load an untagged FIXNUM into a boxed
register.
compiler/arm/call: A couple of VOPs in support of TAIL-LOCAL-CALL.

  * VOPs CURRENT-FP and EMIT-BLOCK-HEADER, largely verbatim copies
from the PPC backend.
compiler/arm/insts: A NULL TN should be valid as immediate data.

  * Reorganize the TN case of ENCODE-SHIFTER-OPERAND to allow for
TNs in the NULL SC to encode as a reference to reg_NULL.
compiler/arm/move: FIXNUM boxing and unboxing.

  * Explain to the compiler how to box and unbox FIXNUMs.  This is
required in order for representation selection to be able to
compute costs for the conversion, even if it doesn't necessarily
call for the conversion to occur.