ARM: cleanup undefined instruction entry code

We don't need to keep reloading the thread into into r10 - we can do
this once and keep the value cached in the register.  Also, schedule
some instructions better so that the pipeline doesn't stall after a
load in the neon code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: mm: Remove unnecessary CMO in Cortex A15 startup

Cortex-A15 flush L2 cache after reset, there is no need to do this
in software, if L2 is already invalidated in bootloader and
cache is disabled. For secondary startup, there is no reason to
flush L2 as well.

This change assumes the setup code is always entered as the result
of CPU reset.

Change-Id: I6d58f8b4a638b70acfb35b97c87a09266aceef41
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/170563
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
ARM: mm: Skip I-cache invalidate for Cortex-A15 boot

This is not required since cache is invalidated by HW in the reset
sequence. Bootloader is supposed to do the same before it hands
over control to kernel.

Change-Id: I0991de3ba1015a32f2c49a0333fd0b17a51a4f31
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/197028
(cherry picked from commit 9c49ffd08d6da03caa820711db83f561d9333aee)
Reviewed-on: http://git-master/r/200854
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: remove unnecessary dcache_clean_area

Cortex-A9 has PIPT D-cache which do not require clean the cache
on creating page table.

Original-Change-Id: I42d528be83ea8def96045c7e575c7b3ed95f5980
Reviewed-on: http://git-master/r/40505
Reviewed-by: Heechul Yun <hyun@nvidia.com>
Tested-by: Heechul Yun <hyun@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R214ce4b138abb18e1cfe79465087c39ead248d72
ARM: LPAE: Invalidate the TLB for module addresses during translation fault

During the free_pgtables() call all user and modules/pkmap entries are
removed. If a translation fault for the modules/pkmap area occurs before
we switched away from the current pgd, do_translation_fault() would copy
the init_mm pud into the user pud.

There is a small window between pud_clear() and pmd_free_tlb() in
free_pmd_range() where the pud entry was cleared but the TLB has not
been invalidated yet and the CPU may have cached the original (valid)
pud entry in the TLB. A scenario like below would get stuck in
continuous prefetch abort:

1. Current process exiting. The modules pmd entries not populated
2. exit_mmap() -> ... -> pmd_free_tlb()
3. pud_clear() for the 1GB pud containing user stack and modules (no TLB
   invalidation yet)
4. Interrupt -> module interrupt routine
5. Level 2 (pmd) translation fault occurs when executing the module
   interrupt routine. The CPU previously cached (TLB) the old valid pud
   value for the modules area, so we don't get a level 1 translation
   fault
6. do_translation fault() copies the pud_k into the pud
7. Linux returns to the faulty instruction. Goes back to 5

At point 7, since the CPU still has the old pud value, it goes back to
point 5 and never gets out of this loop. With this patch, the stale pud
TLB entry is invalidated after point 6 and the subsequent prefetch abort
doesn't occur.

Reported-by: Tony Thompson <Anthony.Thompson@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit bb2c1f205618083611d044a461e019c26468a231)

Rebase-Id: R9afbe63e26001dc849f8c55d5f34d6f5e70cfc47
ARM: mm: cache-l2x0: Implement outer_clean_all()

There is already implemented full outer clean routine in
arch/arm/mm/cache-l2x0.c.

Make it possible to use it through outer_cache interface,
like other outer maintenance functions.

bug 983964

Change-Id: I47f1fad536c151c255e6a42d6517114c334ddfef
Reviewed-on: http://git-master/r/116074
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
Tested-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Justin Paver <jpaver@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rf769958fea9fd10058a4805eeafe08f5f0e895dd

Conflicts:
	arch/arm/mm/cache-l2x0.c
ARM: dma: Drop GFP_COMP for DMA-IOMMU memory allocations

dma_alloc_coherent wants to split pages after allocation in order to
reduce the memory footprint. This does not work well with GFP_COMP
pages, so drop this flag before allocation.

This patch is ported from arch/avr32
(commit 3611553ef985ef7c5863c8a94641738addd04cff).

Change-Id: I67eb2b15807c36c6a3ade95ee35bf5856d8e0e11
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>

Rebase-Id: Rf13a569ebe836d341cf4d9287ff4b4711dde85cc
ARM: cache-l2x0: get size of outer cache

Implement interface for getting size of outer cache.

bug 983964

Change-Id: If855f32d3eaa4c673c132b1964a46fe1c15b4dfe
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/140024
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

Rebase-Id: R11f28e4f625d2626a7a9270265a485e9b07c473f

Conflicts:
	arch/arm/mm/cache-l2x0.c
ARM: 7650/1: mm: replace direct access to mm->context.id with new macro

The mmid macro is meant to be used to get the mm->context.id data
from the mm structure, but it seems to have been missed in a cuple
of files.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: mm: enable non-cacheable streaming enhancement

This is cortex-a15 specific

bug 1178938

Change-Id: Id695d89dbe1411d277f2c1296c74586ca9c1584e
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/164168
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
ARM: mm: Enable NCSE feature for A15 only

Change-Id: If966ee69f1d5e4314f79685238ecff3c44eadac0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/167879
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
ARM: mm: adding a check for slab objects in flush_dcache_page

A page struct obtained via virt_to_page from a slab object may be passed to
the flush_dcache_page function. However, slab allocation is a kernel feature
(can only be done in kernel space) and thus slab objects are never mapped into
user space. However, slab allocators may use the mapping field for their own
purposes and as a result mapping may not be NULL although the page is not
mapped. For this purpose there is a BUG_ON inside page_mapping() to check for
slab objects. So, using NULL for this special case and avoiding calling
page_mapping() on slab objects to avoid the BUG_ON.

Bug 845618.
Bug 1154527.

Reviewed-on: http://git-master/r/45000
(cherry picked from commit 10476ddb84f04bc6c37f8d9ecc15849178a59801)

Reviewed-on: http://git-master/r/189451
(cherry picked from commit 77bfc049878e8c69a36f82a46e32816a72e93214)

Change-Id: If728399cdc6b82be55e4b09f20149e03e196a056
Signed-off-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-on: http://git-master/r/190573
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: Export LoUIS flush

Export flushing to LoUIS.

Change-Id: If9e3b7119dd4dbe7bdcf6caee5e1632e77b2c288
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/379551
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
ARM: kgdb: ignore breakpoint instructions from user mode

Avoid conflicts with user mode usage of the same instructions, as with
Clang -ftrapv.

Change-Id: I12d1c6d8f94376bfd2503cb0be843d7e478fb6ea
Signed-off-by: Todd Poynor <toddpoynor@google.com>
ARM: Honor udelay convention for timer-based delay

Replaced strict "below" comparison in timer delay function with "below
or equal". The former may result in actual delay time below requested
(if the delay happens to start just before cycle counter advance). The
latter guarantees actual delay at/above requested.

Change-Id: I8cf87836e37647997ca6480c2476255369e8953d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/262858
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>