mach-bcm2708: account for FIQ latency in timer interrupt setup

If all of the following happen in a perfect storm:
- A FIQ is taken between readl(stc) and writel(stc + cycles,stc3)
- The timer compare increment is of the order of min_delta_ns
- The FIQ takes longer than the current min_delta_ns value for the timer
  (with contended L1 and L2 caches, 1 in 1000 cases)

Then a stale value will be written to STC3, which will only trigger an
interrupt when STC wraps - in about 71 minutes.

Check after writing the value that STC hasn't run ahead.