board: silkscreen labelling; ~90% done.
schematics, board: labelling, tweaks, polish.
board: round pads, not long; layout tweaks; polish.
board: labelling, layout tweaks, polish.
board: spaced routing between PLCCs; more ground pour.
board, library: more ground around 6522 and PORT B traces.
board: routing minor tweaks; ROM, 74HC00, ...
board: credits text moved to clea vias.
board: minor tweaks to keep text off vias.
board: v1 text in copper, top layer, bottom right.
board, library: pda6502 has tStop layer, not tCream.
schematics, board: v1 gerber files as submitted to Seeed.