CHROMIUM: config: Add a rockchip splitconfig

This doesn't actually boot a rockchip board yet (we need some patches
backported to enable drivers), but it's good to get a baseline in to
try to avoid needing to rebase local config changes over and over
again.

I've verified that after this change generated configs are only
different for "arm generic".  That's different because I added
rockchip features there.  Note that the ARM generic is still not
tested other than just compile testing.

Note that I took DEBUG_LL out of the generic ARM config since I'm not
exactly sure how it would work in a multi-platform config.

BUG=chrome-os-partner:30167
TEST=Compile test generic ARM; with future WIP patches verify booting to
serial on a Rockchip board.

Change-Id: I6a15ba576e4e78c9cdb0632dfd6248f1fa72256c
Signed-off-by: Doug Anderson <dianders@chromium.org>
UPSTREAM: dt-bindings: sram: describe option to reserve parts of the memory

Some SoCs need parts of their sram for special purposes. So while being part
of the peripheral, it should not be part of the genpool controlling the sram.

Therefore add the option to define reserved regions as subnodes of the
sram-node similar to defining reserved global memory regions.

Originally
Suggested-by: Rob Herring <robherring2@gmail.com>

Using subnodes for reserved regions
Suggested-by: Grant Likely <grant.likely@linaro.org>

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I3a96788cf122c5ff36004b79c8e66f0803e61eec
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 96328cdae38c491c69981fa0a6b448c2bc021065)
UPSTREAM: misc: sram: implement reserved sram areas

This implements support for defining reserved areas as subnodes,
to keep the genpool from using these.

Suggested-by: Rob Herring <robherring2@gmail.com>
BUG=chrome-os-partner:30167
TEST=None

Change-Id: I25192ef761f075cb2a1712e7effae15d92b4adeb
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 2da19688f4776437597c1e217d27f74ffaecd52a)
UPSTREAM: ARM: rockchip: add snoop-control-unit

This adds the device-node and config select to enable the
scu in all Rockchip Cortex-A9 SoCs.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I4c62372f0bb77c416a8e212cbf846e57a4c38436
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit f6f70cf707a4774d881cc6274c1b53f0e82d2233)
UPSTREAM: ARM: rockchip: add sram dt nodes and documentation

Add dt-nodes for the sram on rk3066 and rk3188 including the reserved section
needed for smp bringup.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: Ia3e874e39bd9da5394d29fe37d42472cffc10c3c
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit de18e01478d3a65112521de04b67e9029b99f55d)
UPSTREAM: ARM: rockchip: add power-management-unit

The pmu is needed to bring up the cores during smp operations and later
also other system parts. Therefore add a node and documentation for it.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I5c032b23123d98343097a6fbeba2df1fd44ee836
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 46b8219c519be424ab96b5b7fabee171c1e6b4c7)
UPSTREAM: ARM: rockchip: add smp bringup code

This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.

We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done later.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I7ea764d7fbc57e473ea7c48e5c5e7b870ad937b6
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit a7a2b3118b410fb3cd3a8363b157c56f4211ee05)
UPSTREAM: ARM: rockchip: fix copy'n'paste error in smp error messages

The error emitted when mapping the pmu failed, wrongly mentions the sram.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I78211e936b765d91b560cbbebfcbc7c2c6449742
Reported-by: Kent Borg <kentborg@borg.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 5c4348c1f959234664e4667f428cf82b3b8a7c2c)
UPSTREAM: devicetree: bindings: Document Krait/Scorpion cpus and enable-method

Scorpion and Krait don't use the spin-table enable-method.
Instead they rely on mmio register accesses to enable power and
clocks to bring CPUs out of reset. Document their enable-methods.

Cc: <devicetree@vger.kernel.org>
BUG=chrome-os-partner:30167
TEST=None

Change-Id: Ied1aa31b2c15d79fef1e8d17e14230d1a1307c58
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
[sboyd: Split off into separate patch, renamed methods to
match compatible nodes]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit b00c927d06855be4f1aa3d6931cb07fd641c8d8c)
UPSTREAM: ARM: mvebu: use CPU_METHOD_OF_DECLARE for SMP on Armada XP

This commit adds the CPU_METHOD_OF_DECLARE declaration for the Armada
XP SMP operations. Note that the .smp_ops field of Armada XP
DT_MACHINE structure is kept, in order to ensure we remain compatible
with older Device Trees that do not include the "enable-method"
property for the CPUs.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I79e48d27a1d3dea5f36d2b541d8800c0bd72618a
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 2c9b2240bee340711048589023eb057f23fda356)
UPSTREAM: ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE

With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I20a8f29fcea840f0244a9f2b444c242072b32b03
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 26ab69cb4c1f77060bece483f2ec210163867782)
UPSTREAM: pinctrl: rockchip: fix offset of mux registers for rk3188

The correct value of .mux_offset for rk3188 seems to be 0x60
instead of 0x68.

Heiko adds:

GPIO0 only has the second two IOMUX registers:
- GRF_GPIO0C_IOMUX at 0x68
- GRF_GPIO0D_IOMUX at 0x6c
which I guess is where my mistake comes from.

It looks like there does no iomux register exist at all
for the first 16 pins.

In any case, the current number is wrong, and the 0x60
offset is the correct one, but I guess we need to
determine what the affected pins do - do they always have a
gpio mux or such?

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I5e623dc2537c0fe5022b12e8989cb76fe7cad832
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 22c0d7e36f74352f7b80679003bf7edf85736b2b)
UPSTREAM: pinctrl: rockchip: add return value to rockchip_set_mux

In a following change, rockchip_set_mux gets the possibility to fail.
Therefore add a return value to it and honor error codes in functions
using rockchip_set_mux.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: Ia04db878c3f9fba68915eceef9f533f01f15072e
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 14797189b35e9ec4344eeb75bdca4120cba88b69)
UPSTREAM: pinctrl: rockchip: handle first half of rk3188-bank0 correctly

The first half of pinbank 0 only has one muxing function (as gpios) and
does not have a special mux-register.

Therefore ensure that no other mux function can be selected and also do not
write to a non-existent register.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I05062282cac1985d01f25852af20bd948c4ba732
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit c4a532dee6b6e433d267d76d643e62ab90ca9eb9)
UPSTREAM: ARM: rockchip: rk3188: enable pull-ups on UART RX pins

The default behaviour of the uart-rx pins on the rk3188 is to be pulled up and
a lot of designs use diodes to even prevent them from being raised from the
outside.

Therefore change the rx-pin settings accordingly.

This also fixes a uart receive problem on mass production Radxa Rock boards.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I56e91c19338a03f947e30832cf5d7aa05e7f7c0c
Signed-off-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 6faff9b6bd3d2a279b806d721bb2257fdd2e6bf2)
UPSTREAM: pinctrl: rockchip: return a complete config in pinconf_get

Till now pinconf_get only set the argument value into the config parameter
effectively removing the actual config param value. As other pinctrl drivers
do, it might be nicer to keep the config param intact.
Therefore construct a real pinconfig value from param and arg in pinconf_get

BUG=chrome-os-partner:30167
TEST=None

Change-Id: Ib03f2d91b448b10e79617b158f2f8ba9cbfee48e
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit dab3eba7c13cff58dbff767dd02ffb847255ddd3)
UPSTREAM: pinctrl: rockchip: implement PIN_CONFIG_OUTPUT handling

In some cases it is nice to be able to simply control a gpio output
via the PIN_CONFIG_OUTPUT option without having a driver control it.
Thus add support for it to the rockchip pinctrl driver.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I3ddd72f410d33c4b2f9a7560b726f123d10dda8c
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit a076e2ed3fd26f8877a3a010e3fae6b5306ba1b0)
UPSTREAM: pinctrl: rockchip: do not require 2nd register area

Deprecate secondary register area for rk3188 pulls. Instead use big enough
initial mapping of grf registers to catch all.

The now deprecated register is still supported though.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: Id8999ee8b4658cf724b97f02fc023c3ec74027ca
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit bfc7a42a0e74f0b589a017679620d2a3edda9198)
UPSTREAM: pinctrl: rockchip: use regmaps instead of raw mappings

This allows us to use syscons in the future.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I0b09bcba9936295f837565ccadcc9ef7b497f72c
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 751a99aba47e9bd30b4fd5bf36f4e0143d3e81bb)
UPSTREAM: pinctrl: rockchip: rockchip_pinctrl in rockchip_get_bank_data

Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because
later on we need to check a value from it when registering the gpio banks.

BUG=chrome-os-partner:30167
TEST=None

Change-Id: I8b66800161d337e906ba2eae976e55fec1a228f7
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 622f32372bf0592f062c413a91bda6433d5a0147)