OMAP4460: add Reverse Body-Bias support to ABB LDO

On 4460 all OPPs have pre-determined states for VDD_MPU's ABB LDO,
except for OPP_TURBO.  OPP_TURBO may require bypass, FBB or RBB
depending on a combination of characterisation data blown into eFuse
register CONTROL_STD_FUSE_OPP_DPLL_1.

Bits 18 & 19 of that register signify DPLL_MPU trim (see
arch/arm/mach-omap2/omap4-trim-quirks.c).  OPP_TURBO might put MPU's ABB
LDO into bypass or FBB based on this value.

Bit 20 siginifies if RBB should be enabled.  If set it will always
override the values from bits 18 & 19.

The table below captures the valid combinations:

Bit 18 | Bit 19 | Bit 20 | ABB type
0        0        0        bypass
0        1        0        bypass  (invalid combo)
1        0        0        FBB     (2.4GHz DPLL_MPU)
1        1        0        FBB     (3GHz DPLL_MPU)
0        0        1        RBB
0        1        1        RBB     (invalid combo)
1        0        1        RBB     (2.4GHz DPLL_MPU)
1        1        1        RBB     (3GHz DPLL_MPU)

This patch introduces ABB type detection into the ABB init code and
makes a few changes to the ABB programming code to allow for RBB (which
was previously unsupported).

This patch also changes OPP_TURBO's default abb_type to FAST_OPP (FBB)
by default.  This tiny optimization benefits production silicon by
removing one PRCM register write from the ABB initialization code for
the common case where the DPLL_MPU trim values are blown in and the
silicon is weak or nominal (uses FBB at OPP_TURBO).

Change-Id: I73973ddbb77dd89a7e2809bc56d935767f20a5d8
Signed-off-by: Mike Turquette <mturquette@ti.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c