Remove testcase from README which we didn't get. We do get it now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215699 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: implement MRS/MSR (banked reg) system instructions.

These are system-only instructions for CPUs with virtualization
extensions, allowing a hypervisor easy access to all of the various
different AArch32 registers.

rdar://problem/17861345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215700 91177308-0d34-0410-b5e6-96231b3b80d8