i965: Add defines for all new Gen7/8 URB opcodes

Tessellation needs to emit URB reads and atomics;

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Add 64-bit dirty flag handling to brw_upload_pull_constants

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Add PATCHLIST_n to primitives
i965: Add defines for tessellation stages

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Set core tessellation-related limits

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Add backend structures for tess stages

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Add state bits for tess stages

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Add device limits for tess threads & URB entries

The exact limits will need to be revisited once everything works.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
i965: URB allocations for tessellation

V3: Also setup URB semaphores area.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Set tessellation state.

Conflicts:
	src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
	src/mesa/drivers/dri/i965/brw_wm_surface_state.c
i965: Add tessellation shader state bits.

V2 [Chris]: Update for new constants upload mechanism.
fixups
tess vue map setup
initial hs/ds code generation