libbladeRF: Added additional elaboration to SC16Q11 format
hdl: Added option to divide sample counter by two

The sample counter increments once per I and once per Q. However,
the host side will want timestamps that increment once per entire
sample.
hdl: Fixed timestamp readback.

Inserted an appropriate handshake to the time_tamer module for reading
back the current timestamp of either the TX or RX timestamp.
hdl: Fixed timing issue in time_tamer.vhd

Some bits of the timestamp values were reading out incorrectly.
Registered the output on the rising edge of the clock to address this.
hdl: Making some timestamp changes.
hdl: Adding TX NOW and RX metadata gating.

Adding a zero sample to the beginning of the burst tests so initial
power out from the LMS is minimized.

I tried adding a single sample to the DAC output but it didn't seem
to want to work appropriately, so there is around 700us worth of output
power after an initial boot of the board and loading of the FPGA.
hdl: Sending a few more samples when first enabled

Helps mitigate the high default output power from the LMS after
initialization of the device.  The observed time appears <200us.
hdl: Keeping contnuity of RX samples.

During an RX sample overflow, keeping the metadata timestamp and
the sample stream in-sync with each other.
hdl, libbladeRF: Bumped FPGA version to v0.1.0

Minor revision bumped to denote the addition of backwards-compatible
features:
    - Added divide-by-two option for sample counter
    - TX_NOW operation
libbladeRF: Removed SC16_Q12 reverse compat macro

This has been scheduled for removal since RC1 and RC2.
libbladeRF: Updated outdated comments

The situation has changed since thread-safety changes in 7b0cc24f.
libbladeRF: Added API definition for FPGA counter mode enable bit
libbladeRF: Introduced timestamp metadata support for sync data i/f

API support for timestamp metadata has been introduced. This is made
available when using the newly introduced BLADERF_FORMAT_SC16_Q11_META
format value.

When using the synchronous interface, metadata is exchanged between the
caller and the API via the updated bladerf_metadata structure. Users of
the asynchronous interface must currently manually manage the metadata
headers as desired, as documented in libbladeRF.h.

When using the BLADERF_FORMAT_SC16_Q11_META format in conjunction with
the synchronous interface, it is possible to retrieve the timestamp for
received samples and an indication of overrun.  An RX operation may also
be scheduled for at a specific timestamp value the future.  Similarly,
bursts of samples can be scheduled to be transmitted at a specific
timestamp value, or at the first available timestamp ("now").
libbladeRF: Added more complete examples for the synchronous interface

The existing bladerf_sync_rx() snippet in the libbladeRF API docs has
been replaced by a more complete snippet in libbladeRF/doc/examples.

From now on, major snippets and examples to be included in
Doxygen-generated documentation shall now be placed in the
libbladeRF/doc/examples directory, and must be buildable and testable.

The Doxygen "snippet" command to shall be used to include the relevant
code from the example program.

libbladeRF: [WIP] Use a simple delay to wait for TX samples in example
libbladeRF: Made enumeration value references Doxygen links
libbladeRF: Fixed CMakeLists.txt regression (enabling sync verbosity)

ENABLE_LIBBLADERF_SYNC is no longer used, as this interface is now
always present. Since this CMake variable is no longer set, this was
preventing ENABLE_LIBBLADERF_SYNC_LOG_VERBOSE from taking effect.
libbladeRF: Clarified "new version detected" version messages

Instructing the users to notify developers isn't helpful if the user is
simply on an older libbladeRF version. These messages have been changed
to just describe the situation.

These are now also INFO rather than WARNING to be less obnoxious in
cases where users are already aware of the situation and know that
their FPGA/Firmware is compatible, but cannot update libbladeRF.
(For example, they're running a live image and want some FPGA fixes.)