(hls backend) add ram and corresponding write and read indexes
(hls backend) increment read and write indexes at the end of the action
(hls backend with RAM) add unitary test benchs
(hls backend with ram) add actor test benchs
(hsl backend with ram) actor network testbench
(hls backend with ram) correct bug
(hls backend with ram) correct case actor with multiple inputs and
outputs
(hls backend with ram) correct bug
(hls backend with ram)
(hls backend with ram) add batch commande for each instance and correct
bug in case of instance with multiple inputs and outputs port (test ok
for simple example)
(hls backend with ram) correct bug
(hls backend with ram) correct bug in batch command and broadcast test
ok
(hls backend with ram) correct bugs
(hls backend with ram) correct case when actor hs FSM
(hls backend with ram) add actor that write in the ram and an actor that
read from the ram in the case of a port that belong to the network.
Hence change the structure of the Top VHDL of the network
(hls backend with ram) change device in each actor script
(hls bachend with ram) change buffer size
(hls backend RAM) correct case actor has streams and rams
(hls backend with ram) fix ram size 8192
(hls backend with ram) change device from XC7VX330T to XC7V2000T