msm: kgsl: Add the buffer user address to the debugfs memory list

For each buffer in the debugfs memory list print the address it is
mapped to in the user process.  This is useful for matching up the
user side allocations with what the kernel thinks it has.

Change-Id: Ic0dedbadd07a8f704c0bf73b183aaeeddbbdd129
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: kgsl: use %pK to restrict printing GPU / memory addresses

Use %pK in the output for the per-process memory dump to keep from
printing the GPU and user memory addresses for the GPU memory
objects own by the process.  This allows us to make the 'mem' file
world readable without exposing any really dangerous information.

Change-Id: Ic0dedbad21654110905d1b3744f562966584d8ed
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
Perf: Check perf activity on correct CPU

The CPU hotplug notifier is not always preempt safe.
So relying on smp_processor_id() is not correct.

Use the cpu id from the notifier as the target
CPU to check for perf activity before hotplug or power
collapse.

Change-Id: I1a96b236904a2c8ae2f82bbceab4ca8a195395d1
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Add L1 counters to tracepoints

Create a new tracepoint to get L1 PMU counter
information at every context switch. Counters
are captured only when the tracepoint is enabled
via perf or ftrace.

Change-Id: If05527b29e04c700170cfdf9f88d300b2f558ffa
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Fix counts across power collapse

After entry and exit from power collapse, the perf pm_notifier was
calling perf_pmu_disable/enable functions from perf core. Perf core
maintains a counter that it uses to match disable and enable calls but
since pm_notifier is invoked asynchronously, the counter was getting a
non-zero value which prevented the pmu from being enabled. As a result of
this, we were seeing zero counts for some cores across power collapse.

Make the architecture specific calls directly from pm_notifier.

Change-Id: I744e190906a20e70e1e4798235215c385018b121
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Perf: Make per-process counters configurable

Add feature to enable/disable per-process tracecounters at run-time.

Change-Id: Id6a4c7a0ecd1f5add85464c6ed260860e15c4e3b
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
msm: perf: Add L2 support for tracecounters

Add L2 counter output to the tracecounters implementation.
This enables collection of L2 PMU counter values upon context switch.
Set up filtering based on number of L2 counters and number of cores.
Read L2 counter values and display them along with L1 counter values.

Change-Id: I8bbbd251ee52c66505d22ccf037c601013a916f0
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
cfg80211: fix possible circular lock on reg_regdb_search()

When call_crda() is called we kick off a witch hunt search
for the same regulatory domain on our internal regulatory
database and that work gets kicked off on a workqueue, this
is done while the cfg80211_mutex is held. If that workqueue
kicks off it will first lock reg_regdb_search_mutex and
later cfg80211_mutex but to ensure two CPUs will not contend
against cfg80211_mutex the right thing to do is to have the
reg_regdb_search() wait until the cfg80211_mutex is let go.

Change-Id: Ibb44a5325876d77f1549d3938d56d8fbd051b9ba
CRs-Fixed: 655287
Signed-off-by: Santhosh Kumar Padma <skpadma@codeaurora.org>
wcnss: Log debug registers when receives certain notification

If powering on a subsystem during restart fails, SSR framework will send
a "powerup failure" notification to the subsystem. Add support that
WCNSS platform driver will register to listen the notifications and if
receives "powerup failure" notification, it will log the debug registers.

Change-Id: I0ae8a5ee96122d71c7a86711044f6b07e400b62c
Signed-off-by: Yue Ma <yuem@codeaurora.org>
[smihir@codeaurora.org: removed powerup failure notification for riva]
Signed-off-by: Mihir Shete <smihir@codeaurora.org>
wcnss: add API to check if wcnss is undergoing an SSR

Wlan driver should not read registers from wcnss or
try to communicate with the chip when it is undergoing
a subsystem-restart. Added an API with the wcnss platform
driver to check if ssr is in progress, this API will be
used by the wlan driver to protect register access and
other prohibited operations.

Change-Id: Ia0d93e774af126d84dbaabf5c36a2c90fdbd58be
CRs-Fixed: 621974
Signed-off-by: Mihir Shete <smihir@codeaurora.org>
msm: kgsl: Setup a3xx protection in its start function

Setup the protection registers for a3xx towards the end of its
start function instead of doing it in generic ringbuffer start

Conflicts:
	drivers/gpu/msm/adreno_ringbuffer.c

Change-Id: I66df496afa5d1fdf7dea790306f5358c2098674d
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Enable protected register mode for A3XX

Turn on protected register mode for the A3XX GPU family and add 0x63
(RBBM_INT_0_MASK) to the list of protected registers.

Conflicts:
	drivers/gpu/msm/adreno.h
	drivers/gpu/msm/adreno_a3xx.c
	drivers/gpu/msm/adreno_ringbuffer.c

Change-Id: Ic0dedbad10ebfa6eb6d3d815b5aa9b6b6f0e8e35
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Protect SMMU registers from being written by the GPU

Put the SMMU register range in protected mode to shield them from
IB1/IB2 writes from userspace.

CRs-Fixed: 599971
Change-Id: Ic0dedbad8c03fc1c54ff73221231e2440d3c34dd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Print the register that causes a protected mode error

When we get a protected mode error print out the register information
that caused the exception.

Change-Id: Ic0dedbad4f586c5715669226619b51665ef9681f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Protect CP_STATE_DEBUG_INDEX

Put CP_STATE_DEBUG_INDEX and CP_STATE_DEBUG_DATA under protection
to keep it from being written from an IB1. Doing so however opens
up a subtle "feature" in the microcode: memory read opcodes turn off
protected mode in the microcode to do the read and then turns it
back on regardless of the initial state. This is a problem if the
memory read happens while protected mode is turned off and then we
try to access a protected register which then complains and goes boom.

To account for this irregularity explicitly turn back off protected
mode in all the places where we know this will be a problem.

Conflicts:
	drivers/gpu/msm/adreno.c
	drivers/gpu/msm/adreno_a3xx.c

Change-Id: Ic0dedbad1397ca9b80132241ac006560a615e042
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Mark the IOMMU setstate memory as read only

Mark the IOMMU setstate memory as read only in the pagetable.

Change-Id: Ic0dedbadb19e499c749cd744c3e89be3bcb4c2a2
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
msm: kgsl: Enable protected register mode for A2XX

Turn on protected register mode for the A2XX GPU family.

Change-Id: Iecf88d648c9f86faef4fa53e90c2ce81101c58fa
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
'Revert "msm: camera: Enable interrupts before returning during Invalid Image mode."

This reverts commit e6f398d23b8a7ad154ad1f9a7e7c9ae4d6f0b22f.

Change-Id: Ib18e458055695322cf34c73da5e7113ec7ee6cbd
Signed-off-by: Vijaya Kumar T M <vtmuni@codeaurora.org>
msm: camera: Enable interrupts before returning during Invalid Image mode.

CRs-Fixed:649474
Change-Id: Ifd77870dc888232ddc665e0e29974aa6d23db77e
Signed-off-by: Vijaya Kumar T M <vtmuni@codeaurora.org>
msm: msm_fb: set dma pan info when continuous splash is enabled.

Enable vsync_enable flag when continous splash is present. This is
needed to program Tearcheck params for command mode panels.

Change-Id: Ia704b9076628e20a308fbac6f202fa7d20f5f966
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>