* texi2pod.pl (postprocess): Move command process for '@sc' to the
	front of '@dfn'.  Add a new command process for '@t{...}', just print
	the content.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213808 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-11  Richard Biener  <rguenther@suse.de>

        PR fortran/61950
	* trans-expr.c (gfc_conv_structure): Initialize _size with
	a value of proper type.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213809 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/62070
	* tree-ssa-loop-manip.c (gimple_duplicate_loop_to_header_edge):
	Remove SSA checking.

	* gcc.dg/pr62070.c: New testcase.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213810 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
        * common/config/i386/i386-common.c
	(OPTION_MASK_ISA_AVX512BW_SET) : Define.
	(OPTION_MASK_ISA_AVX512BW_UNSET): Ditto.
	(OPTION_MASK_ISA_AVX512VL_UNSET) : Ditto.
	(ix86_handle_option): Handle OPT_mavx512bw.
	* config/i386/cpuid.h (bit_AVX512BW): Define.
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512bw,
	set -mavx512bw accordingly.
	* config/i386/i386-c.c (ix86_target_macros_internal): Handle
	OPTION_MASK_ISA_AVX512BW.
	* config/i386/i386.c (ix86_target_string): Handle -mavx512bw.
	(ix86_option_override_internal): Define PTA_AVX512BW, handle
	PTA_AVX512BW and OPTION_MASK_ISA_AVX512BW.
	(ix86_valid_target_attribute_inner_p): Handle OPT_mavx512bw.
	* config/i386/i386.h (TARGET_AVX512BW): Define.
	(TARGET_AVX512BW_P(x)): Ditto.
	* config/i386/i386.opt: Add mavx512bw.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213811 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-11  Felix Yang  <fei.yang0953@gmail.com>

	PR tree-optimization/62073
	* tree-vect-loop.c (vect_is_simple_reduction_1): Check that DEF1 has
	a basic block.

	* gcc.dg/vect/pr62073.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213812 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
        * common/config/i386/i386-common.c
	(OPTION_MASK_ISA_AVX512VL_SET): Define.
	(OPTION_MASK_ISA_AVX512F_UNSET): Update.
	(ix86_handle_option): Handle OPT_mavx512vl.
	* config/i386/cpuid.h (bit_AVX512VL): Define.
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512vl,
	set -mavx512vl accordingly.
	* config/i386/i386-c.c (ix86_target_macros_internal): Handle
	OPTION_MASK_ISA_AVX512VL.
	* config/i386/i386.c (ix86_target_string): Handle -mavx512vl.
	(ix86_option_override_internal): Define PTA_AVX512VL, handle
	PTA_AVX512VL and OPTION_MASK_ISA_AVX512VL.
	(ix86_valid_target_attribute_inner_p): Handle OPT_mavx512vl.
	* config/i386/i386.h (TARGET_AVX512VL): Define.
	(TARGET_AVX512VL_P(x)): Ditto.
	* config/i386/i386.opt: Add mavx512vl.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213813 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/62075
	* tree-vect-slp.c (vect_detect_hybrid_slp_stmts): Properly
	handle uses in patterns.

	* gcc.dg/vect/pr62075.c: New testcase.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213815 138bc75d-0d04-0410-961f-82ee72b054a4
Replacement of isl_int by isl_val

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213816 138bc75d-0d04-0410-961f-82ee72b054a4
	* lib/target-supports.exp (check_effective_target_arm_thumb1_ok,
	check_effective_target_arm_thumb2_ok): Test with code that passes
	an argument and returns a result.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213818 138bc75d-0d04-0410-961f-82ee72b054a4
	* gcc.target/arm/frame-pointer-1.c: Skip if Thumb is not supported.
	* gcc.target/arm/pr56184.C: Likewise.
	* gcc.target/arm/pr59896.c: Likewise.
	* gcc.target/arm/stack-red-zone.c: Likewise.
	* gcc.target/arm/thumb-find-work-register.c: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213819 138bc75d-0d04-0410-961f-82ee72b054a4
	PR target/62038
	* config/pa/pa.c (pa_asm_output_mi_thunk): Use a branch with %r31 link
	register.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213829 138bc75d-0d04-0410-961f-82ee72b054a4
compiler: Change return type comma-ok assignments to untyped bools.

Fixes https://code.google.com/p/go/issues/detail?id=8476. The test will be submitted once this is fixed in gc and go/types.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213832 138bc75d-0d04-0410-961f-82ee72b054a4
compiler: Change return type comma-ok assignments to untyped bools.

Fixes https://code.google.com/p/go/issues/detail?id=8476. The test will be submitted once this is fixed in gc and go/types.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213833 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/constraints.md (wh constraint): New constraint,
	for FP registers if direct move is available.
	(wi constraint): New constraint, for VSX/FP registers that can
	handle 64-bit integers.
	(wj constraint): New constraint for VSX/FP registers that can
	handle 64-bit integers for direct moves.
	(wk constraint): New constraint for VSX/FP registers that can
	handle 64-bit doubles for direct moves.
	(wy constraint): Make documentation match implementation.

	* config/rs6000/rs6000.c (struct rs6000_reg_addr): Add
	scalar_in_vmx_p field to simplify tests of whether SFmode or
	DFmode can go in the Altivec registers.
	(rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field.
	(rs6000_setup_reg_addr_masks): Likewise.
	(rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p
	field, and wh/wi/wj/wk constraints.
	(rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and
	the wh/wi/wj/wk constraints.
	(rs6000_preferred_reload_class): If SFmode/DFmode can go in the
	upper registers, prefer VSX registers unless the operation is a
	memory operation with REG+OFFSET addressing.

	* config/rs6000/vsx.md (VSr mode attribute): Add support for
	DImode.  Change SFmode to use ww constraint instead of d to allow
	SF registers in the upper registers.
	(VSr2): Likewise.
	(VSr3): Likewise.
	(VSr5): Fix thinko in comment.
	(VSa): New mode attribute that is an alternative to wa, that
	returns the VSX register class that a mode can go in, but may not
	be the preferred register class.
	(VS_64dm): New mode attribute for appropriate register classes for
	referencing 64-bit elements of vectors for direct moves and normal
	moves.
	(VS_64reg): Likewise.
	(vsx_mov<mode>): Change wa constraint to <VSa> to limit the
	register allocator to only registers the data type can handle.
	(vsx_le_perm_load_<mode>): Likewise.
	(vsx_le_perm_store_<mode>): Likewise.
	(vsx_xxpermdi2_le_<mode>): Likewise.
	(vsx_xxpermdi4_le_<mode>): Likewise.
	(vsx_lxvd2x2_le_<mode>): Likewise.
	(vsx_lxvd2x4_le_<mode>): Likewise.
	(vsx_stxvd2x2_le_<mode>): Likewise.
	(vsx_add<mode>3): Likewise.
	(vsx_sub<mode>3): Likewise.
	(vsx_mul<mode>3): Likewise.
	(vsx_div<mode>3): Likewise.
	(vsx_tdiv<mode>3_internal): Likewise.
	(vsx_fre<mode>2): Likewise.
	(vsx_neg<mode>2): Likewise.
	(vsx_abs<mode>2): Likewise.
	(vsx_nabs<mode>2): Likewise.
	(vsx_smax<mode>3): Likewise.
	(vsx_smin<mode>3): Likewise.
	(vsx_sqrt<mode>2): Likewise.
	(vsx_rsqrte<mode>2): Likewise.
	(vsx_tsqrt<mode>2_internal): Likewise.
	(vsx_fms<mode>4): Likewise.
	(vsx_nfma<mode>4): Likewise.
	(vsx_eq<mode>): Likewise.
	(vsx_gt<mode>): Likewise.
	(vsx_ge<mode>): Likewise.
	(vsx_eq<mode>_p): Likewise.
	(vsx_gt<mode>_p): Likewise.
	(vsx_ge<mode>_p): Likewise.
	(vsx_xxsel<mode>): Likewise.
	(vsx_xxsel<mode>_uns): Likewise.
	(vsx_copysign<mode>3): Likewise.
	(vsx_float<VSi><mode>2): Likewise.
	(vsx_floatuns<VSi><mode>2): Likewise.
	(vsx_fix_trunc<mode><VSi>2): Likewise.
	(vsx_fixuns_trunc<mode><VSi>2): Likewise.
	(vsx_x<VSv>r<VSs>i): Likewise.
	(vsx_x<VSv>r<VSs>ic): Likewise.
	(vsx_btrunc<mode>2): Likewise.
	(vsx_b2trunc<mode>2): Likewise.
	(vsx_floor<mode>2): Likewise.
	(vsx_ceil<mode>2): Likewise.
	(vsx_<VS_spdp_insn>): Likewise.
	(vsx_xscvspdp): Likewise.
	(vsx_xvcvspuxds): Likewise.
	(vsx_float_fix_<mode>2): Likewise.
	(vsx_set_<mode>): Likewise.
	(vsx_extract_<mode>_internal1): Likewise.
	(vsx_extract_<mode>_internal2): Likewise.
	(vsx_extract_<mode>_load): Likewise.
	(vsx_extract_<mode>_store): Likewise.
	(vsx_splat_<mode>): Likewise.
	(vsx_xxspltw_<mode>): Likewise.
	(vsx_xxspltw_<mode>_direct): Likewise.
	(vsx_xxmrghw_<mode>): Likewise.
	(vsx_xxmrglw_<mode>): Likewise.
	(vsx_xxsldwi_<mode>): Likewise.
	(vsx_xscvdpspn): Tighten constraints to only use register classes
	the types use.
	(vsx_xscvspdpn): Likewise.
	(vsx_xscvdpspn_scalar): Likewise.

	* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi,
	wj, and wk constraints.
	(GPR_REG_CLASS_P): New helper macro for register classes targeting
	general purpose registers.

	* config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode
	direct moves.
	(zero_extendsidi2_lfiwz): Use wj constraint for direct move of
	DImode instead of wm.  Use wk constraint for direct move of DFmode
	instead of wm.
	(extendsidi2_lfiwax): Likewise.
	(lfiwax): Likewise.
	(lfiwzx): Likewise.
	(movdi_internal64): Likewise.

	* doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and
	wk constraints. Make the wy constraint documentation match them
	implementation.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213834 138bc75d-0d04-0410-961f-82ee72b054a4
Revert last change.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213835 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-11  Joel Sherrill <joel.sherrill@oarcorp.com>

	* s-osinte-rtems.adb: Correct formatting of line in license block.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213840 138bc75d-0d04-0410-961f-82ee72b054a4
Daily bump.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213845 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-12  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    PR middle-end/62103
    * gimple-fold.c (fold_ctor_reference): Don't fold in presence of
    bitfields, that is when size doesn't match the size of type or the
    size of the constructor.

    gcc/testsuite/
    PR middle-end/62103
    * gcc.c-torture/execute/bitfld-6.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213846 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
	* config/i386/i386.c (standard_sse_constant_opcode): Use
	vpxord/vpternlog if avx512 is availible.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213847 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-12  Yury Gribov  <y.gribov@samsung.com>
    
gcc/
	* internal-fn.c (init_internal_fns): Fix off-by-one.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@213848 138bc75d-0d04-0410-961f-82ee72b054a4