ARM: mm: implement LoUIS API for cache maintenance ops

ARM v7 architecture introduced the concept of cache levels and related
control registers. New processors like A7 and A15 embed an L2 unified
cache
controller that becomes part of the cache level hierarchy. Some
operations in
the kernel like cpu_suspend and __cpu_disable do not require a flush of
the
entire cache hierarchy to DRAM but just the cache levels belonging to
the
Level of Unification Inner Shareable (LoUIS), which in most of ARM v7
systems
correspond to L1.

The current cache flushing API used in cpu_suspend and __cpu_disable,
flush_cache_all(), ends up flushing the whole cache hierarchy since for
v7 it cleans and invalidates all cache levels up to Level of Coherency
(LoC) which cripples system performance when used in hot paths like
hotplug
and cpuidle.

Therefore a new kernel cache maintenance API must be added to cope with
latest ARM system requirements.

This patch adds flush_cache_louis() to the ARM kernel cache maintenance
API.

This function cleans and invalidates all data cache levels up to the
Level of Unification Inner Shareable (LoUIS) and invalidates the
instruction
cache for processors that support it (> v7).

This patch also creates an alias of the cache LoUIS function to
flush_kern_all
for all processor versions prior to v7, so that the current cache
flushing
behaviour is unchanged for those processors.

v7 cache maintenance code implements a cache LoUIS function that cleans
and
invalidates the D-cache up to LoUIS and invalidates the I-cache,
according
to the new API.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>

Signed-off-by: Paul Reioux <reioux@gmail.com>

Conflicts:
	arch/arm/mm/cache-v7.S