Created a makefile for intel testing x86 and 64
Added x86::IMUL32rr Opcode
Merge branch 'x86' of https://github.com/draperlaboratory/fracture into x86
Adding opcodes for x86::add32rr x86::add32mi8.  These opcodes are not stable yet
Minor changes
Reducing ADD32rr - still crashing...
Reworked x86::IMUL32rr and it appears to be working.  Need to add more before Ops before I can visually confirm
Fixed x86::SHLD32rri8 - the way I have been handling constants has been flawed
Fixing small copy & paste bug
Added X86::CMP32mr - extremely similar to CMP32rm except registers are in different places
Added X86::JB_1
Starting X86::MOV8ri.  This OpCode down converts an i32 to an i8 and I think the down conversion is currently broken.  The freebee version doesn't work.
Added an IREmitter::visitMul - that fixed an implementation error.  Working to resolve an intermittant crash; which still exists in the same context - the x86 specific version changes should be better since X86::MOV32rr now has an SDLOC
Not building yet...  Makeing large changes to properly handly ISD::BRCOND IR.  Currently having a linker issue in Decompile header, this object has been building.  Once this object is building, and Decompiler is further integrated into structure we should be able to get the instruction size to properly (and abstractly) calculate where we want to branch to.  The decompiler has this information because it is calculated to get to the next instruction.
Further into build process.  Need a few more additions for brcond to work.
Leaving x86 branch in a buildable state
Implemented general purpose branch code.  Note - this code is rather simplistic right now.  I don't think have properly abstracted signed and unsigned differences yet.
Frank & I added X86::MOV8ri OpCode
Working through more OpCodes and the IREmitter.  The BRCond IREmitter is not working as it should, needs to be redone.
The majority of this commit revolves around branching.  The X86 branching process relies on the EFLAGS register which in certain optimization circumstances can make the process more complicated.  This code brings the original X86IREmitter::visitBRCOND back as visitBRCONDBasic, the addition is X86IREmitter::visitBRCONDAdvanced that handles situations where the EFLAGS register is being more directly manipulated.  The Advanced version is not complete yet.