Add support for C-coded AXI4 slave devices.
Simbus support for Xilinx PCIe core

This is the start, with the first attempts at simulating the
Xilinx PCIe core. This implements simple configuration reads.
Add vpi_flush after error message so that messages are not lost.
Xilinx_pcie_slot pass through TLPs

The user needs to see TLPs, this passes them through, and
also offers the means to get TLPs out from user code. Note
that config TLPs that are used by the slot are not passed.
The simbus Xilinx-pcie bus is really a pcie-tlp bus

Turns out that the server interface that I'm using is exactly the
TLP protocol carried over a 64bit AXI4-Stream pair. So rename the
internal ports appropriately. The good news is this will allow for
generic TLP interface slots as well.
Get write TLPs all the way to the target user mode.
simbus support for pcie-tlp read messages.
Xilinx PCIe slot better manages tx port arbitration.

Use stateful arbitration that is aware of the user requests
even when the cfg_gnt is permanently active.