Fixed bug with lb and lh, debugging sw and sb.

May need to go back to clocking every component for things to work
right. always @ sensitivity tests seem to fail in data memory when
trying to read and write data. Implement ALU and Control logic for
additional instructions.
Fixed timing issue with clocking.

Need to determine if the PC is technically incrementing correctly.
Should the address be the current instruction or the next one during the
cycle?
Implemented more instructions.

Still working on Beq, j, sll and srl (need to pass shamt into ALU), jr
and jal.