lpc_uart: fix combinational loop
mil: do not use data input as clock line
scu: declare mil clock inputs as asynchronous to wishbone system clock
monster: power_test was missing default value
pexaria5: cut butis and ref clock domains

Peter's core crosses signals between these domains.
The crossing is made safe by a state machine.
vetar: cut butis and ref clock domains
submodules: get fixes from cern
Merge branch 'asterisk' into proposed_master

Conflicts:
	top/gsi_vetar/wr_core_demo/vetar_top.sdc