ENGR00169489-2 Add OV5642 csi camera support for i.mx6 sabre-lite board.

Add OV5642 csi camera support for i.mx6 sabre-lite board

Signed-off-by: Yi Li <R80015@freescale.com>
ENGR00171544 usb-core: usb host will be broken after system pm test

At i.mx6q sabrelite, there is a usb hub on board. After several
suspend suspend/resume iterations, the usb host will be broken.
It is IC limitation, and similar with:
574b9641d5846e58273dac6bf80fcf1ff312c5c9

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: make shi <b15407@freescale.com>
ENGR00170453-1 ssi: disable ssi2 clk after probe

disable ssi2 clk after init ssi.

Signed-off-by: Gary Zhang <b13634@freescale.com>
ENGR00171792: MX6Q_ARD: fix the pad setting conflicts between can0 and enet

1. need add 'can0' in kernel commandline to enable can1,
the default enet is enabled, can2 is not affected by this.
2. add  MX6Q_PAD_SD2_DAT0__GPIO_1_15 back in pad setting,
as this is required for enet rework.
   add 4.7k pull down and GPIO_1_15 will reset the u39,
   to make it functional, we need pull high.
3. the ENET PHY steering is configured by u39 setting.

Signed-off-by: Hake Huang <b20222@freescale.com>
ENGR00171708: [v2] Remove build warnings in ENGR00170444

Remove ddc_dvi_init and ddc_dvi_update functions because
    those generate a compiler warning.
Also remove I2C duplicate IOMUXES and devices.

Signed-off-by: Israel Perez <B37753@freescale.com>
ENGR00171622 - FEC : workaround for Gb enet in sabrelite board.

Micrel phy KSZ9021 Gb speed cannot work well in i.MX6 sabrelite
board. Advertise PHY is not 1000Base-T capable.

If nfs boot kernel, phy will work at 100Mbps, or else phy will
work at Gbps mode. And if hot-plugin cable, phy will work at Gbps
mode. Enet can work well in all of them.

But in Gbps mode, uDMA sometime cannot write  frame "L" bit in
exuberate transfer, so driver will print some warning message:
"FEC ENET: rcv is not +last"

Signed-off-by: Fugang Duan  <B38611@freescale.com>
ENGR00171731 ipuv3 dev: add time statistic for each task

add time statistic for each task

Signed-off-by: Jason Chen <b02280@freescale.com>
ENGR00171116 [MX6]Remove unnecessary workaround for suspend/resume

The root cause of suspend/resume fail has been found,
the i-cache should be invalidated before resume. So
the workaround can be removed.

Signed-off-by: Anson Huang <b20788@freescale.com>
ENGR00171890 [MX6Q_ARD]fix the boot fail when otg power is not initialized

Add u43 setting back

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Hake Huang <b20222@freescale.com>
ENGR00171383 HDMI: blank and unblank display can not resume.

It cause by HDMI Blank/Unblank function not implement.
Implement the HDMI blank/unblank function.

Signed-off-by: Sandor Yu <R01008@freescale.com>
ENGR00171949:gpu-viv: change from mutex to completion for waiting pm events

viv code is using mutex to wait for pm events,
kernel will see this as a dead lock and give a warrning, as the mutex
can be hold for a long time.

Signed-off-by: Wu Guoxing <b39297@freescale.com>
Acked-by: Lily Zhang
ENGR00171462-1 vpu: add BIT_PIC_RUN register in mxc_vpu.h

Add BIT_PIC_RUN register definition in mxc_vpu.h of arch/arm

Signed-off-by: Sammy He <r62914@freescale.com>
ENGR00171462-2 vpu: fix vpu cannot run after suspend/resume

This patch fix vpu cannot run issue after suspend/resume
with stop mode. Need to re-load vpu firmware if current PC
is zero.

Signed-off-by: Sammy He <r62914@freescale.com>
ENGR00172175 MX6Q: OV5640_MIPI support fast configure

OV5640_MIPI need to be configure faster to get capture image
quickly. So change the configures, when change the resolution
OV5640_MIPI sensor will not do reset.

Signed-off-by: Even Xu <b21019@freescale.com>
ENGR00169906-1 GPMI : set the GPMI to 20M by default

The 11M for GPMI is too slow.

Change the GPMI to 20MHz by default, most of the NAND
chips can run with this frequency.

Signed-off-by: Huang Shijie <b32955@freescale.com>
ENGR00169906-2 GPMI : setup the TIMING1 for ready/busy

The TIMING1 specifies the timeouts used when monitoring the
NAND READY pin and IOWAIT signals.

We should set a default value for it.

Signed-off-by: Huang Shijie <b32955@freescale.com>
ENGR00169906-3 MXS-DMA : add new flags

We catch a DMA timeout bug in the NAND in mx6q.

If we do not set the WAIT4END in the middle DMA command structure
of the long DMA command chain, a DMA timeout may occurs.

In order to fix the bug, we should let the driver to
set the proper DMA flags in the DMA command structrues.

So add the new flags for MXS-DMA.

The driver can use these flags to control the DMA in a flexible way.

Signed-off-by: Huang Shijie <b32955@freescale.com>
ENGR00169906-4 MXS-DMA : change the last parameter of mxs_dma_prep_slave_sg()

For a long DMA chain which may have more then two DMA Command Structures,
the current DMA code sets the WAIT4END bit at the last one, such as:

+-----+		      +-----+			   +-----+
| cmd | ------------> | cmd | ------------------>  | cmd |
+-----+		      +-----+			   +-----+
						       ^
						       |
						       |
						      set WAIT4END here

But in the NAND ECC read case, the WAIT4END bit should be set
not only at the last DMA Command Structure, but also at the middle one,
such as:

+-----+		      +-----+			   +-----+
| cmd | ------------> | cmd | ------------------>  | cmd |
+-----+		      +-----+			   +-----+
                         ^                            ^
			 |                            |
			 |                            |
			set WAIT4END here too        set WAIT4END here

We set the WAIT4END in the middle DMA Command Structure to ensure
the BCH module finishs its job. If we do not wait in this situation,
the BCH module may be changed in the following DMA Command Structures,
and it maybe becomes unstable which will cause a DMA timeout
This has been catched in the MX6Q board.

So rewrite the last parameter of mxs_dma_prep_slave_sg().
Add some more flags to let the driver sets the WAIT4END as it needs.

Acked-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
ENGR00169906-5 GPMI : change the code for new interface

If we do not set the WAIT4END in the middle DMA command structure
of the long DMA command chain, a DMA timeout may occurs.

The reason of the DMA timeout is:
	[1] We do not set the WAIT4END in the DMA command structure
	    which do the ECC READ PAGE by the BCH.
	[2] So the following DMA command structure (maybe in other DMA
		CHAIN)may disable the BCH module.
	[3] If the time delay between [2] and [1] is long enough,
	    it's ok. But if the time delay is not long enough, the BCH
	    module may become unnormal, so it can not finish its job.
	    The DMA will timeout in this case.

We have changed the DMA interface to fix the bug, now use the new
interface.

Acked-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
ENGR00172008 HDMI audio continues playing after doing ctrl-z

The bug is that HDMI audio continues playing after doing ctrl-z,
repeating playing a small part of the buffer.

Mask HDMI audio irq when we receive SNDRV_PCM_TRIGGER_STOP command.
Unmask when we receive SNDRV_PCM_TRIGGER_START.

Signed-off-by: Alan Tull <r80115@freescale.com>