add :otherwise option to deftypes case macros

git-svn-id: http://acl2-books.googlecode.com/svn/trunk@2976 303c5b2c-9740-0410-b014-fd8f9db7be32
VL: unify var/netdecl representation

This is mostly groundwork toward supporting the richer port syntax for
SystemVerilog.
  - Do away with vl-netdecl-p, in favor of vl-vardecl-p.
  - Extend datatypes with a new nettype case
  - Fix up portdecl-sign to be more general
  - Update everything accordingly

This incidentally adds support for verilog-2005 'output reg', 'output integer',
and 'output time' declarations (fixes issue 84).

git-svn-id: http://acl2-books.googlecode.com/svn/trunk@2977 303c5b2c-9740-0410-b014-fd8f9db7be32