fixed osccal to be more tolerant of reset timing
littlewire- packet format was incorrect

WS2812 data ttransfer was using a SETUP IN transfer into a 8 byte
buffer. Lots of useless USB traffic.
polled usb part I
make u-wire micronucleus compliant again

Micronucleus "patched" the interrupt address. So trying to store data in
flash memory pos 4 and 5 is bound to fail.
reduced stack usage in receiver routine
No more register saving in receiver routine
reduce receiver size
fewer bytes
shorter crc
shorter osccal, removed nops after osccal write
main -> 1014 bytes
usbdrv: cleaned up and optimized assembler code
usrdrv: oscalasm adapted for attiny10
usbdrv: usbconfig for attiny 10
crt1.s for attiny10
main.c with attiny 10 adaptions
main.c: littlewire firmware version reply
updated with version info request