ASoC: Intel: Revisit Baytrail reset and boot logic

Debugging DSP double reseting has shown that different delays nor setting
reset bit after stall bit in sst_byt_reset() seems not to help DSP re-reset
issues. More over one reference code is doing it in the same way than this
function was doing originally but without any delay.

Then sst_byt_boot() was more interesting. It appeared that CSR register
reads there are very sensitive after releasing the stall. In current form
PWAITMODE was zero immediately but turned on somewhere later. If there was
a delay after releasing the stall and then subsequent CSR reads the DSP
appeared to be lost completely. The same reference is also doing DSP boot
differently: it sets all reset, reset vector and stall bits again and then
clears reset and stall without a delay between these operations.

Therefore change the sst_byt_reset() and sst_byt_boot() to behave like the
reference code. It appears DSP sends the FW init complete message now
when doing second reset but IPC commands to DSP will timeout.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>