msm_serial_hs: Manage clock path-vote correctly

clock path vote is needed for core and iface vote,
so remove it after these votes are removed, and
make sure clock path vote/unvote are balanced by
removing unnecessary clock path vote

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm_serial_hs: Avoid RX getting stuck during rapid clock on/off

Due to race conditions in clock off and clock on sequence
BAM RX descriptor doesn't get queued or may get queued multiple
times. These issues may showup when the client issues rapid clock-on
clock-off operations.
This patch optimizes clock-off sequence while synchronizing clock
off/on with the BAM RX callback (In BAM RX callback, Forcestale
is not issued for every BAM RX callback).

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm_serial_hs: Race Condition during Baud Rate Configuration

Race Condition:
==============
CPU 0:
1.) Rx BAM pipe got disconnected during Baud Rate Cnfg
2.) Rx tasklet got scheduled
3.) Tasklet is issuing Rx command to BAM
4.) BAM API aquired spinlock and accessed Null Pointer
This lead to Null Pointer Access and Crash
CPU 1:
5.) As part of baud rate configuration process CPU 1
called BAM Rx Connect API
6.) BAM API is trying acquire Spinlock
7.) Spinlock is not released by CPU0
This lead to BUG ON

Fix:
===
During Baud Rate Configuration, if Rx command is queued
set the flag for not issuing any Rx command to BAM
Adding rx_cmd_exec variable to avoid command getting
queued twice without callback for the first

Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm_serial_hs: Program RFR to synchronize clock-off sequence with HW

Assert the RFR line during clock off and de-assert
it after the clock off is successful. This is to avoid
the data to be coming from the client during clock off.

Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm_serial_hs: Programing the TX FIFO watermark level to 4

As per the Hardware Data Book recommendation the
TX FIFO watermark level should not be zero.
Hence programing the TX FIFO watermark level to
4 to avoid corner cases

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm_serial_hs: Remove code dependency on flag tty_flush_receive

Removing code dependency on the flag and check the
circular buffer directly and make sure that spin lock is taken
appropriately in the tx lower half.

This avoids the condition that can cause
1. tx lower half
2. submit tx command
to race.

Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm_serial_hs: Programming BCR Register

UART Core is showing inconsistent behaviour in firing
Stale Timeout Interrupt. Stale Timeout is not happening
at some points. After programming the BCR register the
Stale Timeout is happening as expected.
Also fix the BCR register offset to avoid instablilities when
console is disabled.

Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
msm_serial_hs_lite: Cleanup

Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>