ARM: net: JIT compiler for packet filters

based of Matt Evans's PPC64 implementation.

The compiler generates ARM instructions but interworking is
supported for Thumb2 kernels.

Supports both little and big endian. Unaligned loads are emitted
for ARMv6+. Not all the BPF opcodes that deal with ancillary data
are supported. The scratch memory of the filter lives on the stack.
Hardware integer division is used if it is available.

Enabled in the same way as for x86-64 and PPC64:

	echo 1 > /proc/sys/net/core/bpf_jit_enable

A value greater than 1 enables opcode output.

Signed-off-by: Mircea Gherzan <mgherzan@xxxxxxxxx>
---

Changes in v7:
 * fix the intruction generation for LDX_MSH, OR_X, LSH_K,
   RSH_K and JMP_JA
 * fix the condition for saving the A register
 * use fls() instead of the compiler builtin
 * punt to the interpreter on absolute loads with K < 0
 * check for invalid data references
 * support the NEG opcode
 * clear X in the prologue based on a context flag
 * simplify the conditional jumps

Changes in v6:
 * fix the code generation for the ANC_CPU opcode

Changes in v5:
 * replace SEEN_LEN with SEEN_SKB
 * set ctx->seen when handling some ancillary data opcodes

Changes in v4:
 * first check if the JIT compiler is enabled
 * fix the code generation for the LDX_MSH opcode

Changes in v3:
 * no longer depend on EABI and !Thumb2
 * add BLX "emulation" for ARMv4 without Thumb
 * use the integer divide instruction on Cortex-A15
 * fix the handling of the DIV_K opcode
 * use a C wrapper for __aeabi_uidiv
 * fix the generation of the epilogue (non-FP case)

Changes in v2:
 * enable the compiler only for ARMv5+ because of the BLX instruction
 * use the same comparison for the ARM version checks
 * use misaligned accesses on ARMv6
 * fix the SEEN_MEM
 * fix the mem_words_used()

Conflicts:
	arch/arm/Kconfig
	arch/arm/Makefile
ARM: OMAP4: Only wait for module ready for clocks enabled via MODULEMODE

Some clocks are enabled by programming the MODULEMODE bit field of the PRCM
CLKCTRL registers. For these clocks, we should wait for the module to
transition from the idle state when we enable them. For other clocks, such as
optional clocks, that are enabled via other bits in the CLKCTRL registers, the
idle state is not updated when we enable them and so we should not wait for
the idle state to change when we enable them. This is causing unnecessary
delays to occur when enabling optional clocks as we are waiting for the idle
state to change and eventually timeout.

Change-Id: Iaa8a86d38a55b4faa95988c48e4bac0e772c7492
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Huzefa Kankroliwala <huzefank@ti.com>
backing-dev: use synchronize_rcu_expedited instead of synchronize_rcu

backing-dev: use synchronize_rcu_expedited instead of synchronize_rcu

synchronize_rcu sleeps several timer ticks. synchronize_rcu_expedited is
much faster.

With 100Hz timer frequency, when we remove 10000 block devices with
"dmsetup remove_all" command, it takes 27 minutes. With this patch,
removing 10000 block devices takes only 15 seconds.

Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Jens Axboe <jaxboe@fusionio.com>
(cherry picked from commit ef3230880abd36553ab442363d3c9a0661f00769)
net: Compute protocol sequence numbers and fragment IDs using MD5.

Computers have become a lot faster since we compromised on the
partial MD4 hash which we use currently for performance reasons.

MD5 is a much safer choice, and is inline with both RFC1948 and
other ISS generators (OpenBSD, Solaris, etc.)

Furthermore, only having 24-bits of the sequence number be truly
unpredictable is a very serious limitation.  So the periodic
regeneration and 8-bit counter have been removed.  We compute and
use a full 32-bit sequence number.

For ipv6, DCCP was found to use a 32-bit truncated initial sequence
number (it needs 43-bits) and that is fixed here as well.

Reported-by: Dan Kaminsky <dan@doxpara.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 6e5714eaf77d79ae1c8b47e3e040ff5411b717ec)

Conflicts:

	drivers/char/random.c
	net/ipv4/route.c
tcp: RFC2988bis + taking RTT sample from 3WHS for the passive open side

This patch lowers the default initRTO from 3secs to 1sec per
RFC2988bis. It falls back to 3secs if the SYN or SYN-ACK packet
has been retransmitted, AND the TCP timestamp option is not on.

It also adds support to take RTT sample during 3WHS on the passive
open side, just like its active open counterpart, and uses it, if
valid, to seed the initRTO for the data transmission phase.

The patch also resets ssthresh to its initial default at the
beginning of the data transmission phase, and reduces cwnd to 1 if
there has been MORE THAN ONE retransmission during 3WHS per RFC5681.

Signed-off-by: H.K. Jerry Chu <hkchu@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 9ad7c049f0f79c418e293b1b68cf10d68f54fcdb)
cpufreq: intelliactive: initial coding and introduction!

intelliactive is based on Latest Google Interactive cpufreq governor from
Google.  The original Interactive provides smooth UI operations but suffers
slight battery drain due to its aggressive policies.  Intelliactive is an
improvement built on top of it.

It has the following enhancements added:
1. self-boost capability from input drivers (no need for PowerHAL assist)
2. two phase scheduling (idle/busy phases to prevent from jumping directly to
   max freq
3. Checks for offline cpus and short circuits some unnecessary checks to
   improve code execution paths
4. removed trace calls

Signed-off-by: Paul Reioux <reioux@gmail.com>

Conflicts:
	drivers/cpufreq/Kconfig
	drivers/cpufreq/Makefile
	include/linux/cpufreq.h
intelliactive: backport to Linux 3.0.x / Linux 3.1.x kernels

Signed-off-by: Paul Reioux <reioux@gmail.com>
intelliactive: tune for OMAP2 SOCs

Signed-off-by: Paul Reioux <reioux@gmail.com>
intelliactive: rework input register/unregister

Signed-off-by: Paul Reioux <reioux@gmail.com>
enable intelliactive