Removed line in Vec.scala to not generate ROMs, because it breaks verilog
Merge branch 'master' into dse
Added flags to call Params.dump and Params.load from chiselMain
Fixed mismatched type issue
Fixed misspelling of 'flattenning'
Relocated jackhammer functions into chisel
Added Jackhammer.scala to implement jackhammer functionality, including dumping and loading .prm files
Merge branch 'master' of https://github.com/ucb-bar/chisel into dse

Conflicts:
	src/main/scala/Vec.scala
A large commit:
 -Added oscar lib for constraint solving for Jackhammer
 -Refactored Jackhammer to plug into oscar
 -Refactored Param classes to enable constraints between parameters
 -Changed serialization and deserialization to work with new parameters
Cleaned up filename of design.prm files
Merge branch 'master' of github.com:ucb-bar/chisel into dse
Catch remaining param classes for cpp generation
Merge branch 'master' of github.com:ucb-bar/chisel into dse
Merge branch 'master' of github.com:ucb-bar/chisel into dse
(Flo) Fix "eq" and "neq" width specification

The meaning of the width paramater in "eq" and "neq" nodes changed at
some point recently -- it used to be that the width was the width of
the input nodes, but now it's the output width.  As the output width
of all comparison operations is always 1 bit, this is pretty useless.

This patch changes back to the old behavior which is both more useful
and works with existing code.
Merge pull request #142 from palmer-dabbelt/eq_width

(Flo) Fix "eq" and "neq" width specification
Merge branch 'master' of github.com:ucb-bar/chisel into dse

Conflicts:
	src/main/scala/hcl.scala