Do a little more work
Fix handling of 32-bit scalar loads.  This worked accidently before, but the strided load case was actually handling it.
Move RTL into v1 directory
Pull in V2 microarchicture
Tweak
Update docs
Update license
Enable v2 testbench to work with cosimulator register checking.
Enable memory dumps for v2 testbench
Allow overriding microarchitecture version in environment
Add load-store cosimulation test and fix v2 arch so it passes it.
Add OP_COPY to V2 uarch.  Augment and add tests.
Get vector integer comparisons working
Fix extension case
Add more single cycle operations (copied from v1)
Fix synthesis errors
Rough in multi-issue instructions (specifically scatter gather loads)
Gather load/scatter store now working
Add test for integer ops and masks. Fix inverted masks.
Add format test