Fixed M95 issue with fdd-4msps-t2r2 script with ADI state machine.
Merge branch 'sdrdc-devel' of https://github.com/silverbullettechnology/sdrdc-build into sdrdc-devel
Updated ADI temperature measurement as per M96
m100: Revised PL and FSBL prebuilts:

- system_0x3425ef27.bit reverts pin assignments from Ethernet testing
- zynq_fsbl-20140331.1.elf revises FPGA clocks:
  - CLK0: 100MHz
  - CLK1: 200MHz
  - CLK2: 200MHz
  - CLK3:  48MHz
Merge sdrdc-devel into sdrdc-staging for RC4 QA