- Fixed an issue with l.sra/l.srai where a shift of 0 set the destination register to 0xffffffff (due to unpredictable C operation usage). Fixes #1.
- Added support for l.lws.
- Branches in a delay slot are no longer executed (think this is the correct behaviour from looking at the OR1KSim instruction set tests).
Merge branch 'master' of https://github.com/davey3000/nacl-openrisc-1000