ARM: OMAP2: convert sys_ck and osc_ck to standard clock types

osc_ck can be simply defined as a multiplexer clock, and the sys_ck
can be a simple divider.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: OMAP2420: clock: get rid of fixed-div property use

Cleans up the code a bit and is useful for clock data DT conversion.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
CLK: TI: DPLL: simplify autoidle register detection logic

AMxxxx dpll_data previously had autoidle_mask set, even if these SoC:s
don't have autoidle register. Remove the bit-field value as it is unused,
also drop the unnecessary DPLL_HAS_AUTOIDLE flag passing during init,
as we can just simply check against the contents of the autoidle_mask.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
CLK: TI: DPLL: add support for omap2 core dpll

OMAP2 has slightly different DPLL compared to later OMAP generations.
This patch adds support for the ti,omap2-dpll-core-clock and also adds
the bindings documentation.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
CLK: TI: APLL: add support for omap2 aplls

This patch adds support for omap2 type aplls, which have gating and
autoidle functionality.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
CLK: TI: gate: fixed DT binding documentation bugs

ti,composite-gate-clock documentation was missing, also the register
offset examples were wrong.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
CLK: TI: interface: add support for omap2430 specific interface clock

OMAP2430 I2CHS modules require specific hardware ops to be used, so added
a new compatible string for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
CLK: TI: OMAP2: add clock init support

Adds support for registering the alias clocks, boot time clock-enable list
and disabling autoidle of clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: OMAP2: PRM: add support for OMAP2 specific clock providers

This patch adds support for initializing also omap2-prcm and omap2-scrm
through DT.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: dts: omap2 clock data

This patch creates a unique node for each clock in the OMAP2 power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: OMAP2: clock: add DT boot support for cpufreq_ck

The clock and clkdev for this are added manually.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
CLK: TI: gate: add composite interface clock to OMAP2 only build

Composite interface clock is needed by OMAP2, but it was only built
in for OMAP3. Fixed the conditional build flag checks for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: OMAP2: clock: use DT clock boot if available

Otherwise legacy boot clock data is used.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: OMAP24xx: clock: remove legacy clock data

This is no longer needed as clock data is provided through DT.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
clk: ti: clk-7xx: Correct ABE DPLL configuration

ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: AM43xx: clk: Change the wdt1 func clk src to per_32k clk

WDT1 module can take one of the below clocks as input functional
clock -
	- On-Chip 32K RC Osc [default/reset]
	- 32K from PRCM

The On-Chip 32K RC Osc clock is not an accurate clock-source as per
the design/spec, so as a result, for example, timer which supposed
to get expired @60Sec, but will expire somewhere ~@40Sec, which is
not expected by any use-case.

The solution here is to switch the input clock-source to PRCM
generated 32K clock-source during boot-time itself.
This is derived from AM33xx clock file.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk

cpsw_cpts_rft_clk has got the choice of 3 clocksources
 -dpll_core_m4_ck
 -dpll_core_m5_ck
 -dpll_disp_m2_ck

By default dpll_core_m4_ck is selected, witn this as clock
source the CPTS doesnot work properly. It gives clockcheck errors
while running PTP.

 clockcheck: clock jumped backward or running slower than expected!

By selecting dpll_core_m5_ck as the clocksource fixes this issue.
In AM335x dpll_core_m5_ck is the default clocksource.

Signed-off-by: George Cherian <george.cherian@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock

To allign the name with the other atl clock names:
atlclkin3_ck -> atl_clkin3_ck

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
dt:/bindings: DRA7 ATL (Audio Tracking Logic) clock bindings

Audio Tracking Logic is designed to be used by HD Radio applications to
synchronize the audio output clocks to the baseband clock. ATL can be also
used to track errors between two reference clocks (BWS, AWS) and generate a modulated
clock output which averages to some desired frequency.
In essence ATL is generating a clock to be used by an audio codec and also
to be used by the SoC as MCLK.

To be able to integrate the ATL provided clocks to the clock tree we need
two types of DT binding:
- DT clock nodes to represent the ATL clocks towards the CCF
- binding for the ATL IP itself which is going to handle the hw
  configuration

The reason for this type of setup is that ATL itself is a separate device
in the SoC, it has it's own address space and clock domain. Other IPs can
use the ATL generated clock as their functional clock (McASPs for example)
and external components like audio codecs can also use the very same clock
as their MCLK.

The ATL IP in DRA7 contains 4 ATL instences.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
clk: ti: Driver for DRA7 ATL (Audio Tracking Logic)

Audio Tracking Logic is designed to be used by HD Radio applications to
synchronize the audio output clocks to the baseband clock. ATL can be also
used to track errors between two reference clocks (BWS, AWS) and generate a modulated
clock output which averages to some desired frequency.
In essence ATL is generating a clock to be used by an audio codec and also
to be used by the SoC as MCLK.

To be able to integrate the ATL provided clocks to the clock tree we need
two types of DT binding:
- DT clock nodes to represent the ATL clocks towards the CCF
- binding for the ATL IP itself which is going to handle the hw
  configuration

The reason for this type of setup is that ATL itself is a separate device
in the SoC, it has it's own address space and clock domain. Other IPs can
use the ATL generated clock as their functional clock (McASPs for example)
and external components like audio codecs can also use the very same clock
as their MCLK.

The ATL IP in DRA7 contains 4 ATL instences.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>