ARM: AM33xx: PRM: make direct register access functions static

These should not be accessed outside driver, thus removed the APIs
from the header file and made the implementation static.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP4: PRM: make omap4_prm_read/write_inst_reg calls static

These are not (and should not be) used by anybody outside the PRM
driver itself.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP3: PRM: make PRCM interrupt handler related functions static

These are not needed outside the PRM driver, so make them static and
remove the prototypes from the public header.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP4: PRM: make PRCM interrupt handler related functions static

These are not needed outside the PRM driver, so make them static and
remove the prototypes from the public header.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP3+: PRM: add generic API for reconfiguring I/O chain

This adds a generic API for reconfiguring the I/O chain. The implementation
will call the SoC specific function registered during init time. The SoC
specific reconfigure functions are also made static, as they don't need
to be accessed outside the PRM driver itself.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Nishanth Menon <nm@ti.com>
[tony@atomide.com: updated for recent omap3 prcm fixes]
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP2+: PRM: provide generic API for system reset

This patch combines the various prm_warm_reset calls under a common
API prm_reset_system, and adds the SoC specific implementation under
prm_ll_data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: integrator: move AP timer to clocksource

This moves the timer/clocksource implementation for the
Integrator/AP down to drivers/clocksource and augments the
driver a little to use CLOCKSOURCE_OF_DECLARE(). Remove
the static mapping of the timer blocks while we're at it.

Tested on the Integrator/AP.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ARM: dts: Fix bootloader version dependencies by muxing n900 smc91x pins

Apparently some versions of nolo don't mux the all the necessary GPMC
pins for the smc91x probe to work properly. Let's fix this issue
by adding mux support for GPMC to the kernel.

Note that GPMC clk needs input enabled for OnenNAND to work.

Cc: Kevin Hilman <khilman@kernel.org>
Cc: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP2+: gpmc: Print error message in set_gpmc_timing_reg()

Simplify set_gpmc_timing_reg() and always print error message
if the requested timing cannot be achieved due to a too fast
GPMC functional clock, irrespective if whether DEBUG is defined
or not. This should help us debug timing configuration issues,
which were otherwise simply not being displayed in the kernel log.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP2+: gpmc: Error out if timings fail in gpmc_probe_generic_child()

gpmc_cs_set_timings() returns non-zero if there was
an error while setting the GPMC timings. e.g. Timing was too
large to be accomodated with current GPMC clock frequency and available
timing range. Fail in this case, else we risk operating a NOR device
with non compliant timings.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices

Although RESET state of LIMITEDADDRESS bit in GPMC_CONFIG register
is 0 (i.e. A26-A11 enabled), faulty bootloaders might accidentally
set this bit. e.g. u-boot 2014.07 with CONFIG_NOR disabled.

Explicity disable LIMITEDADDRESS bit for non NAND devices so that
they can always work.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it

As per the OMAP reference manual [1], the Chip Select must be
disabled (i.e. CSVALID is 0) while configuring any of the
Chip select parameters.

[1] - 10.1.5.1 Chip-Select Base Address and Region Size Configuration
http://www.ti.com/lit/pdf/swpu177

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP2+: gpmc: Sanity check GPMC fck on probe

This prevents potential division by zero errors
if GPMC fck turns out to be zero due to faulty clock
data.

Use resource managed clk_get() API.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
ARM: dts: Fix wrong GPMC size mappings for omaps

The GPMC binding is obviously very confusing as the values
are all over the place. People seem to confuse the GPMC partition
size for the chip select, and the device IO size within the GPMC
partition easily.

The ranges entry contains the GPMC partition size. And the
reg entry contains the size of the IO registers of the
device connected to the GPMC.

Let's fix the issue according to the following table:

Device          GPMC partition size     Device IO size
connected       in the ranges entry     in the reg entry

NAND            0x01000000 (16MB)       4
16550           0x01000000 (16MB)       8
smc91x          0x01000000 (16MB)       0xf
smc911x         0x01000000 (16MB)       0xff
OneNAND         0x01000000 (16MB)       0x20000 (128KB)
16MB NOR        0x01000000 (16MB)       0x01000000 (16MB)
32MB NOR        0x02000000 (32MB)       0x02000000 (32MB)
64MB NOR        0x04000000 (64MB)       0x04000000 (64MB)
128MB NOR       0x08000000 (128MB)      0x08000000 (128MB)
256MB NOR       0x10000000 (256MB)      0x10000000 (256MB)

Let's also add comments to the fixed entries while at it.

Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: dts: Add smc91x GPMC configuration for 2430sdp

Let's use the bootloader values except for the partially configured
wait-pin that does not seem to work.

Cc: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: dts: Add GPMC timings for omap zoom serial port

The four port serial port on the zoom debug board uses a TL16CP754C
with a single interrupt and GPMC chip select. The serial ports each
use a 8 bytes for IO registers, and are 256 bytes apart on the GPMC
line.

Let's add timings for all four ports so we can remove the GPMC
workarounds for using bootloader timings.

Not caused by this patch, but looks like u-boot only properly
initializes the fifo on the first serial port. Currently the other
ports produce garbage at least with my version of u-boot. I suspect
that TL16CP754C needs non-standard initialization added to 8250
driver to properly fix this issue.

Cc: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
dt-bindings: Document Broadcom Cygnus SoC and clocks

Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
ARM: dts: Enable Broadcom Cygnus SoC

DT files to enable cygnus consisting on reference designs
and cygnus core configuration.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
amdkfd: Implement the Get Version IOCTL

Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
ARM: dts: rockchip: Add EMAC Rockchip for RK3066 SoCs

This patch adds the right pins topology for the MAC and MDIO
found in RK3066 SoCs. Boards based on this SoC have an
initial support for the emac-rockchip dt-binding.

Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>