fsl_i2c: add support for 3rd and 4th I2C

Add support for 3rd and 4th I2C.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
mtd: cfi_flash: fix clang warning

clang warns this check is silly; it is since s is
a local variable.

u-boot/drivers/mtd/cfi_flash.c:2363:13: warning: comparison of
  array 's' not equal to a null pointer is always true
  else if ((s != NULL) && (strcmp(s, "yes") == 0)) {

cc: Stefan Roese <sr@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
lib: div64: add missing include

Include the function its prototype to prevent the warning
that it has no prototype.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
arm: m53evk: Fix RTC bus number

A previous update to the I2C stack introduced a typo in the
configuration option. Fix the typo and therefore allow the
RTC to work correctly with the 'date' command again.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
mx6: imx-regs: Remove unused 'omux' field from iomux struct

'omux' field is not used anywhere and such layout is not valid for mx6solox.

Instead of adding more ifdef's into the structure, let's simply remove this
unused 'omux' field.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offset

According to the Reference Manual the 'spdif0_clk_podf' field of register
CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset
definitions accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definition

According to the Reference Manual the 'wb_per_at_lpm' field of register
CCM_CLPCR corresponds to bit 16 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED

According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of
register CCM_CIMR corresponds to bit 19 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
pmic: pmic_pfuze100: Use a shorter name for PMIC name

It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already
know it is a PMIC.

Call it simply 'PFUZE100' instead.

Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
i.MX31 PDK: Enable generic board for i.MX31 PDK

Enable CONFIG_SYS_GENERIC_BOARD for the i.MX31 PDK board.

Tested on actual hardware.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
ARM: mx5: Fix CHSCCDR name

Fix the name of the CCM CHSCCDR register.

Signed-off-by: Marek Vasut <marex@denx.de>
ARM: mx6: Prevent overflow in DRAM size detection

The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
only 3840 MiB of that can be really used. In case the controller is
configured to operate a 4GiB module, the imx_ddr_size() function will
correctly compute that there is 4GiB of DRAM in the system. Firstly,
the return value is 32-bit, so the function will effectively return
zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
of all that. Thus, clamp the returned size to 3840MiB in such case.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
ARM: mx6: Handle the MMDCx_MDCTL COL field caprices

The COL field value cannot be easily calculated from the desired
column number. Instead, there are special cases for that, see the
datasheet, MMDCx_MDCTL field description, field COL . Cater for
those special cases.

Signed-off-by: Marek Vasut <marex@denx.de>
ARM: mx6: Enable Thumb build for SPL

Building the SPL in Thumb mode saves roughly 30% in size of the
resulting SPL binary. As the size of SPL it limited on the MX6,
this helps a lot.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
pci: mx6: fix occasional link failures

According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.

Without this patch we find a high link failure rate (>5%) on certain
IMX6 boards at various temperatures.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6sxsabresd: Update DDR initialization

Use the latest DDR initialization values suggested by the FSL hardware team.

While at it, add some comments for clarification.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6sx: Adjust enable_fec_anatop_clock() for mx6solox

Configure and enable the ethernet clock for mx6solox.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6sxsabresd: Add Ethernet support

mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.

Add support for one FEC port initially.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>