i965: Skip _mesa_load_state_parameters when there are zero parameters.

Saves a tiny bit of CPU overhead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
rtasm,translate: Re-enable SSE on Mingw64.

This reverts f4dd0991719ef3e2606920c5100b372181c60899.

The src/gallium/tests/unit/translate_test.c gives the same results on
MinGW 64-bits as on Linux 64-bits.  And since MinGW is often used for
development/testing due to its convenience, it's better not to have this
sort of differences relative to MSVC.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
i965/disasm: Properly decode branch_ctrl (gen8+)

Add support for decoding the new branch control bit. I saw two things wrong with
the existing code.

1. It didn't bother trying to decode the bit.
-  While we do not *intentionally* emit this bit today, I think it's interesting
   to see if we somehow ended up with the bit set. It may also be useful in the
   future.

2. It seemed to be the wrong bit.
-  The docs are pretty poor wrt which bit this actually occupies. To me, it
   /looks/ like it should be bit 28. I am not sure where Ken got 30 from. I
   verified it should be 28 by looking at the simulator code.

I also added the most basic support for GOTO simply so we don't need to remember
to change the function in the future.

v2:
Move the branch_ctrl check out of the if gen >= 6 check to make it more
readable. (Matt)
ENDIF doesn't have branch_ctrl (Matt + Ken)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i915: Only use TEXCOORDTYPE_VECTOR with cube maps on gen2

Check that the target is GL_TEXTURE_CUBE_MAP before emitting
TEXCOORDTYPE_VECTOR texture coordinates.

I'm not sure if the hardware would like CARTESIAN coordinates
with cube maps, and as I'm too lazy to find out just emit the
VECTOR coordinates for cube maps always. For other targets use
CARTESIAN or HOMOGENOUS depending on the number of texture
coordinates provided.

Fixes rendering of the "electric" background texture in chromium-bsu
main menu. We appear to be provided with three texture coordinates
there (I'm guessing due to the funky texture matrix rotation it does).
So the code would decide to use TEXCOORDTYPE_VECTOR instead of
TEXCOORDTYPE_CARTESIAN even though we're dealing with a 2D texure.
The results weren't what one might expect.

demos/cubemap still works, which hopefully indicates that this doesn't
break things.

Also tested with:
 bin/glean -o -v -v -v -t +texCube --quick
 bin/cubemap -auto
from piglit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
vc4: Update for new kernel ABI with async execution and waits.

Our submits now return immediately and you have to manually wait for
things to complete if you want to (like a normal driver).
radeonsi: use minnum and maxnum LLVM intrinsics for MIN and MAX opcodes

So far it has been compiled into pretty ugly code (8 instructions or so
for either opcode).

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
i965: Combine offset/texture_offset fields.

texture_offset was only used by some texturing operations, and offset
was only used by spill/unspill and some URB operations. These fields are
never used at the same time.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965: Move common fields into backend_instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/fs: Move ip_record class to its one use.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
i965/fs: Remove unused apply_stride().

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
i965/fs: Remove is_valid_3src() checks from emit_lrp.

The visitor emits MOVs to temporary registers for immediates, so these
never trigger. For further proof, check case ir_triop_fma.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
i965/fs: Remove is_valid_3src().

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
i965/vec4: Extract depctrl hazards

Move this to a separate function so that we can begin to add other little
caveats without making too big a mess.

NOTE: There is some desire to improve this function eventually, but we need to
fix a bug first.

v2:
Use const for the inst for the hazard check (Matt)
Invert safe logic to get rid of the double negative (Matt)
Add PRM reference for predicates (Matt)
Add note about empirical evidence for math (Matt)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965/vec4/gen8: Handle the MUL dest hazard exception

Fix one of the few cases where we can't reliable touch the destination hazard
bits. I am explicitly doing this patch individually so it is easy to backport. I
was tempted to do this patch before the previous patch which reorganized the
code, but I believe even doing that first, this is still easy to backport.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
nvc0: define numbers, make code better readable

Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
mesa/gallium: API settings / rasterization rules
nvc0: use API settings / rasterization rules (v2)

v2: dropped part of clip_halfz handling implemented in upstream commit
    3bc42a09e2d13c42e15423a17b5c571049a11224
nv50,nvc0: handle TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION

Allow viewport bypass used by D3D9 applications.
nv50,nvc0: handle NULL vertex elements without fallback

This makes Gallium Nine faster.
nv50/ir/tgsi: implement TGSI_OPCODE_NRM,DP2A

Used by d3d9 st.