- inverted the clkby2 which improves timings and now we meet all the timing requirements on FPGA.
- [Bug] issue when we are in block_state and data from L2 arrives then we return back to block_state but if again data from L2 arrives then we should do mshr_add only after servicing the new request. Earlier we do mshr_add so that when we again return to block_state the block signal remains high and we keep looping in that state. So we changed the mshr_add logic a little bit.
- [Bug] added feature so that if we are not able to write back a dirty line to the L2 as it stalls (when going from READ_WAIT to WB_L2_WAIT state). Then we go back and retry writing back that data by returning to READ_WAIT state. ()
- [Bug]added diff_line_done flag to handle the case when we are in block_state and data from L2 arrives and we have a different line pending. Then we go to IDLE state rather than looping the block_state.
- Decreased cache size as for most of our applications we never need such a big cache.
- [Bug] fixed bug so that when data from L2 or DRAM arrives and we are writing this data to our cache then we always set the valid bit irrespective of mem_valid_o is high or not. See new logic for valid_b_i
small change in testbench, we invert the faster clock