cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API

There are several use cases for performing a certain task when CBMEM is
first set up (usually to migrate some data into it that was previously
kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them
differently: timestamp migration is called explicitly from
cbmem_initialize(), certain x86-chipset-specific tasks use the
CAR_MIGRATION() macro to register a hook, and the CBMEM console is
migrated through a direct call from romstage (on non-x86 and SandyBridge
boards).

This patch decouples the CAR_MIGRATION() hook mechanism from
cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer
description of what it really does. All of the above use cases are
ported to this new, consistent model, allowing us to have one less line
of boilerplate in non-CAR romstages.

BRANCH=None
BUG=None
TEST=Built and booted on Nyan_Blaze and Falco with and without
CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after
boot (and the resume log after S3 resume on Falco). Compiled for Parrot,
Stout and Lumpy.

Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
vboot2: Reduce minimum required work buffer size

Apparently our initial submission of 16K was a little too generous for
the vboot2 work buffer, and I hear that we should also be well within
bounds for 12K. This patch reduces the minimum asserted by memlayout so
some of our low-mem boards can get a few more kilobytes back for
discretionary spending. Also changes the required minimum alignment to 8
since that's what the current vboot code aligns it to anyway, and add a
warning comment to make it clearer that this is a dangerous number
people should not be playing with lightly.

BRANCH=None
BUG=None
TEST=Built and booted on Pinky.

Change-Id: Iae9c74050500a315c90f5d5517427d755ac1dfea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232613
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
rk3288: Add CBMEM console support and fix RETURN_FROM_VERSTAGE

Since we can now reduce our vboot2 work buffer by 4K, we can use all
that hard-earned space for the CBMEM console instead (and 4K are
unfortunately barely enough for all the stuff we dump with vboot2).

Also add console_init() and exception_init() to the verstage for
CONFIG_RETURN_FROM_VERSTAGE, which was overlooked before (our model
requires those functions to be called again at the beginning of every
stage... even though some consoles like UARTs might not need it, others
like the CBMEM console do). In the !RETURN_FROM_VERSTAGE case, this is
expected to be done by the platform-specific verstage entry wrapper, and
already in place for the only implementation we have for now (tegra124).

(Technically, there is still a bug in the case where EARLY_CONSOLE is
set but BOOTBLOCK_CONSOLE isn't, since both verstage and romstage would
run init_console_ptr() as if they were there first, so the romstage
overwrites the verstage's output. I don't think it's worth fixing that
now, since EARLY_CONSOLE && !BOOTBLOCK_CONSOLE is a pretty pointless
use-case and I think we should probably just get rid of the
CONFIG_BOOTBLOCK_CONSOLE option eventually.)

BRANCH=None
BUG=None
TEST=Booted Pinky.

Change-Id: Id666cb7a194d32cfe688861ab17c5e908bc7760d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232614
rk3288: Don't hardcode CONFIG_COLLECT_TIMESTAMPS

CONFIG_COLLECT_TIMESTAMPS seems more like a user-configurable option
than a hardcoded property of the SoC, so let's not select if by default
(this is more in line with previous boards).

BRANCH=None
BUG=None
TEST=Booted Pinky, made sure 'cbmem -t' fails.

Change-Id: I06fc28f4a57a38bdd0be1f98a4766633ccb347ff
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232615
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
veyron: Enable timestamps and CBMEM console

Turn on CBMEM console support now that we have all the pieces in place,
and also (re-)enable timestamps on Pinky (which have previously been
taken out of the config file there, but not on Jerry and Mighty).

BRANCH=None
BUG=None
TEST=Booted Pinky, confirmed 'cbmem -c' and 'cbmem -t' show correct
results (except for the dual init in the bootblock, which CL:231942
will take care of).

Change-Id: I424902f237537c9f1a65b9266a53e971ca25c09e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232616
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Revert "armv7-m: use generic memset, memcpy, memmove"

This reverts commit 0e906536fffa057f22098ec6a4dd6572c419b539.

Change-Id: I81c67b5459a9f7010654e633083812b6ab363e59
Reviewed-on: https://chromium-review.googlesource.com/232930
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
vboot: Include vb2_api.h, instead of lower-level vboot2 header files

This will allow vboot2 to continue refactoring without breaking
coreboot, since there's now only a single file which needs to stay in
sync.

BUG=chromium:423882
BRANCH=none
TEST=emerge-veyron_pinky coreboot
CQ-DEPEND=CL:233050

Change-Id: I74cae5f0badfb2d795eb5420354b9e6d0b4710f7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233051
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Revert "ryu: libpayload: Add CONFIG_LP_TEGRA_VIDEO_CONSOLE_INIT"

This reverts commit c29a5e368d280f999aa64da78c7101222a22d9a0.
This option is not used any longer.

BUG=None
BRANCH=None
TEST=Config not used.

Change-Id: I0718bd701c5588b39b69e36d8e2b510a82cf1372
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233075
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
vboot: Remove unused 2lib header path

Before the change to use vb2_api.h, coreboot needed to know where to
find the vboot2 header files.  Now those are all included by
vb2_api.h, so coreboot doesn't need to know about
firmware/2lib/include (and in fact, the 2lib directory is about to go
away).

BUG=chromium:423882
BRANCH=none
TEST=emerge-veyron_pinky coreboot

Change-Id: I7f69ca9cf8d45c325219efceca0cb8d1340f7736
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233223
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
storm: Fix timer init order problem

Commit 257aaee9e3a (arm: Add bootblock_mainboard_early_init() for
pre-console initialization) inadvertently moved the timer initialization
after console initialization for IPQ806x, which is apparently not a good
idea for this platform. This patch solves the issue by moving
init_timer() to bootblock_mainboard_early_init(), which is the new hook
explicitly provided to perform pre-console tasks.

BRANCH=None
BUG=None
TEST=Built and booted Storm with 257aaee9e reverted. Noticed that it was
already broken. Bisected coreboot and tracked down breakage to commit
a126a62f (ipq8064: use the new utility to build bootblock). Built and
booted successfully with this patch and a revert of a126a62f to confirm
that the bug in question here is fixed.

Change-Id: Ie4aa2d06cb6fda6d5ff8dd5ea052257fb7b8a24b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233290
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
rush: Add gpio config for PWR button and LID open switch

Due to CL https://chromium-review.googlesource.com/231250,
depthcharge now detects gpio state based on gpio configurations
done by coreboot instead of redoing configuration at
depthcharge. However, PWR button and LID open pins have not
been configured in coreboot. So, add the missing code here.
Otherwise, TOT coreboot/depthcharge rush build can not load
in kernel.

BUG=chrome-os-partner:34336
BRANCH=none
TEST=build rush and test with pwr button press and lid switch

Change-Id: I6c322cd987967920f236aae653294db079678408
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/233322
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Baytrail: Update microcode to version 82D

Version 82D of microcode.

BUG=None
TEST=Build + boot on Rambi, verify on console log that revision 82D
microcode is loaded.
BRANCH=Rambi

Change-Id: Ia9c66aeb16d48f7823e64f889a1d468a54216fac
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233473
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Makefile: Fix dependency tracking for ramstage objects

Dependency tracking in incremental builds is currently broken for the
ramstage, due to the intermediate linking step into one ramstage.o file
per directory. The original xxx.ramstage.o files are removed from
ramstage-objs, so they don't end up in allobjs and won't get translated
into DEPENDENCIES. This patch explicitly adds them to DEPENDENCIES
beforehand to resolve the issue.

BRANCH=None
BUG=None
TEST=Built, ran 'touch src/include/cbmem.h' and built again
incrementally. Confirmed that objects dependent on the modified header
such as timestamp.ramstage.o get rebuilt correctly.

Change-Id: Ife529ad8f5c011456c1e0c380356f1b1bb5047cb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233571
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
cbmem: Extend hooks to ramstage, fix timestamp synching

Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common
CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since
timestamp_sync() was no longer called there. Oops.

This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism
to the cbmem_initialize() call in ramstage. The macro is split into
explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as
possible and prevent surprises (although just using a single macro and
relying on the Makefiles to link an object into all appropriate stages
would also work).

This allows us to get rid of the explicit cbmemc_reinit() in ramstage
(which I somehow accounted for in the last patch without realizing that
timestamps work exactly the same way...), and replace the older and less
flexible cbmem_arch_init() mechanism.

Also added a size assertion for the pre-RAM CBMEM console to memlayout
that could prevent a very unlikely buffer overflow I just noticed.

BRANCH=None
BUG=None
TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once
again show up. Compile-tested for Rambi and Samus.

Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
broadwell: Fix incorrect SATA port map mask

WPT-LP has 4 SATA ports. Current code assumes 6 SATA ports and as a result,
some reserved bits are written with 1. No specific issue has been observed
so far.

BUG=None
BRANCH=None
TEST=Verify SATA PCI configure space dump on Auron

Change-Id: I9c53ac86e2bf72901647bd2cfa48ac0ce31abea0
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/233661
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
veyron: Turn off SD card power in romstage

The only way to reliably reset an SD card in an unknown state is by
power-cycling. Since a kernel may crash and reboot at any point, SD
cards may be left in one of them fancy high-throughput modes that
depthcharge (or, in fact, a newly booting kernel without prior
knowledge) doesn't support, so we need to reset the card on every boot.

This patch adds support to turn off an RK808 regulator completely and
uses that to turn off SD card power rails in early romstage. The time
until configure_sdmmc() in ramstage turns them back on should be more
than enough to drain the power rail for an effective power-cycle.

BRANCH=None
BUG=chrome-os-partner:34289
TEST=Booted a Pinky from SD card, noticed that it works before and
after this patch.

Change-Id: I904b2d23ca35f765c000f9bee7637044f674eff9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233713
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
t132: Add I2S1 support to funit

Used for audio on Rush/Ryu. I2S1/DAP2 provides the audio
'stream' for the dev/rec mode 'beeps'.

BUG=chrome-os-partner:32582
BRANCH=none
TEST=With follow-on CLs that make use of this support,
audio beeps (via VbExBeep) can be heard on Rush. Built
both Rush and Ryu OK.

Change-Id: Ia8c32303979f25300e22b5a14609d9d9d5ce3132
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/233670
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
storm: add ipq8064 blobs to the CBFS

Files necessary for the SOC bringup are added to the CBFS as raw
blobs.

Ipq8064 specific MBN header will allow to determine were the blobs
should be loaded and what start address should be used.

BRANCH=storm
BUG=chrome-os-partner:34161
TEST=build storm firmware and verify that the right components are added:
  $ emerge-storm coreboot chromeos-bootimage
  $ cbfstool /build/storm/firmware/image.bin  print
  image.bin: 8192 kB, bootblocksize 32488, romsize 2883584, offset 0x7f40
  alignment: 64 bytes, architecture: arm

  Name                           Offset     Type         Size
  cdt.mbn                        0x7f40     raw          376
  ddr.mbn                        0x8100     raw          25820
  rpm.mbn                        0xe640     raw          78512
  tz.mbn                         0x21940    raw          85360
  fallback/verstage              0x36700    stage        39500
  fallback/romstage              0x401c0    stage        15652
  fallback/ramstage              0x43f40    stage        24328
  config                         0x49e80    raw          2701
  fallback/payload               0x4a940    payload      65592
  u-boot.dtb                     0x5a9c0    (unknown)    2922
  (empty)                        0x5b580    null         2509336
  $

Change-Id: Id642ae68ef07750624f85b31ad891752d8af99bf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
libpayload: add veyron_speedy config

BUG=chrome-os-partner:33269
TEST=emerge-veyron_speedy libpayload
BRANCH=None

Change-Id: Iee749956b6fb44966d02f9684aa68a032eabe844
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/233821
Reviewed-by: Julius Werner <jwerner@chromium.org>
veyron: Add veyron_speedy board

Essentially a copy of veyron_jerry for now

BUG=chrome-os-partner:33269
TEST=emerge-veyron_speedy coreboot
BRANCH=None

Change-Id: Ife457db4fd67fe69bcd4082694b3372eccfb304b
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/233822
Reviewed-by: Julius Werner <jwerner@chromium.org>