vc4: Abstract out the field-merging logic for instructions.

I'm going to be doing the same logic for some more fields next.
vc4: Set unused raddr fields to QPU_R_NOP.

The simulator assertion fails if you have a write to a reg and then a read
(for example, in the NOP side of an instruction), even if the read isn't
used for anything.  By setting unused raddrs to NOP, we avoid the problem
(since only the phsyical registers are tracked).
gallium: Copy fd_lowering.[ch] to tgsi_lowering.[ch] for code sharing.

Lots of drivers need to transform the weird instructions in TGSI into
reasonable scalar ops, and this code can make those translations
canonical.

Acked-by: Rob Clark <robclark@freedesktop.org>
gallium: Reformat tgsi_lowering.c for the normal style.

Acked-by: Rob Clark <robclark@freedesktop.org>
gallium: Rename freedreno parts of tgsi_lowering.[ch].

Acked-by: Rob Clark <robclark@freedesktop.org>
vc4: Start using tgsi_lowering for opcodes we haven't supported before.
vc4: Enable DP lowering in TGSI instead of our own code.
vc4: Enable POW lowering in TGSI instead of our own code.
vc4: Add support for two-sided color.

It's fairly easy, thanks to Rob Clark's lowering code.  Fixes
two-sided-lighting and 4 vertex-program-two-side testcases, while
regressing 8 testcases that involve enabling two-sided color while only
initializing one of the two colors in the VS.  If you're enabling two
sided color, it's of course expected that you really do set up both
colors, so this is still an improvement (and when we set up a linker for
TGSI, we'll hopefully fix those 8 fails).
ilo: fix rectlist on GEN7+

It was broken by 343b014b57ecc5431477e090100e6a26edbda540.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
vc4: Fix scalar math opcodes to replicate their result from the X channel.

Thanks to robclark for pointing out that I was probably failing to do this
when I reported a "bug" in his lowering code.
vc4: Enable LIT lowering in TGSI instead of our own code.

This brings us the -128/128 clamping on the w component.
vc4: Move the mirrored kernel code to a kernel/ directory.

Now this whole setup matches the kernel's file layout much more closely.
vc4: Mostly fix offset calculation for NPOT mipmap levels.

The non-base NPOT levels are stored as POT-aligned images.  We get that
POT alignment by minifying the POT-aligned base level.

This means that level strides are also POT aligned, so we have to tell the
rendering mode config that our resource is larger than the actual
requested area.

Fixes the fbo-generatemipmap-formats NPOT cases.  Regresses
depthstencil-render-miplevels 273 * -- the texture presentation now works
(where it was completely broken before), it looks like there's some
overflow of image bounds happening at the lower miplevels.
vc4: Add some optimization of FADD(FSUB(0, x)).

This is a common production of st_glsl_to_tgsi, which uses negate flags on
source arguments to handle subtraction.
vc4: Optimize SF(ITOF(x)) -> SF(x).

This is a common production of st_glsl_to_tgsi, because CMP takes a float
argument.
r600g,radeonsi: Always use GTT again for PIPE_USAGE_STREAM buffers

Putting those in VRAM can cause long pauses due to buffers being moved
into / out of VRAM.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84662
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
mesa: Make _mesa_print_arrays use stderr.

These days, most driver debug output happens via stderr, not stdout.
Some applications (such as Xephyr) also appear to close stdout which
makes these messages go nowhere.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
i965: Add a BRW_MOCS_PTE #define.

Like BDW_MOCS_WB and BDW_MOCS_WT, this specifies that we want to use all
three caches (L3, LLC, and eLLC where available), but leaves the LLC
caching mode up to the kernel's page table entry.

This allows the kernel to pick WB/WT/UC based on whether it's using a
buffer for scanout.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: mesa-stable@lists.freedesktop.org
i965: Use BDW_MOCS_PTE for renderbuffers.

Write-back caching cannot be used for buffers being scanned out by the
display engine; surfaces used for scan-out must be write-through or
uncached.  I originally chose WT for render targets because it works in
all cases.  However, we really want to use write-back caching where
possible, as it is more efficient.

Most renderbuffers are not used for scanout - off-screen FBOs certainly
are fine, and non-pageflipped backbuffers should be fine as well.  So
in most cases WB will work.  However, we don't know what will be used
for scan-out, so we instead simply use the PTE value specified by the
kernel, as it knows these things.

This matches our MOCS choice on Haswell.

Fixes performance regressions since commit ee4484be3dc827cf15bcf109f5
in a microbenchmark (spotted by Eero Tamminen).  Improves performance
in GLBenchmark 2.7/EgyptHD by 7.44362% +/- 0.496939% (n=55) on a
Broadwell GT2.  Improves performance in a bunch of other microbenchmarks
by ~15% or so.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reported-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: mesa-stable@lists.freedesktop.org