plat-stm: L2CC_MUTEX implementation

Signed-off-by: Pascal Brand <pascal.brand@st.com>
plat-stm: fix TA L1 table handling

bugz: https://bugzilla.bri.st.com/show_bug.cgi?id=6613

There is only 1 mmu table effectively used to map TAs: one
1 at mapped at a given time.

SEC_TA_MMU_TTB_FLD must be aligned, with an alignment constraint
defined from number of 1MB section entries in the user mapping.

SEC_TA_MMU_TTB_FLD could be allocated at run time.

Cleanup linker file: remove useless CTX_MEM and optimize a bit
stacks and mmu tables location.

Reviewed-on: https://gerrit.st.com/17038
Tested-by: Etienne CARRIERE <etienne.carriere@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>
plat-stm: set L2 prefetch offset to 7

Reviewed-on: https://gerrit.st.com/17052
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Etienne CARRIERE <etienne.carriere@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>
plat-stm: clean tz init and l2 init/enable

Useless config of read-only reg SCU_CONFIG.

L2 FLZW feature: must be set in core after L2 is configured
and enable. TZ inits default not set core FLZ. L2 enable
sets core FLZ.

Rename PL310_WAY_SIZE into PL310_LINE_SIZE.

Reviewed-on: https://gerrit.st.com/17060
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Etienne CARRIERE <etienne.carriere@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>