R600/SI: Fix 64-bit bit ops that require the VALU.

Try to match scalar and first like the other instructions.
Expand 64-bit ands to a pair of 32-bit ands since that is not
available on the VALU.
R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.

No longer asserts, but now you get moves loading legal immediates
into the split 32-bit operations.
R600/SI: Fix extra mov from legalizing 64-bit SALU ops.

Check the register class of each operand individually
to avoid an extra copy to a vgpr.